Comtech EF Data SNM-1001L - Manual (Page 16)

SNM-1001L Satellite Modem Revision 1
Preface MN/SNM1001L.IOM
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Figures
FIGURE 1-1. BLOCK DIAGRAM..........................................................................................................................1–2
FIGURE 1-2. DEMODULATOR BLOCK DIAGRAM ..........................................................................................1–9
FIGURE 1-3. M&C BLOCK DIAGRAM..............................................................................................................1–12
FIGURE 1-4. DIMENSIONAL ENVELOPE DRAWING ....................................................................................1–14
FIGURE 2-1. INSTALLATION OF THE OPTIONAL MOUNTING BRACKET KT/6228-1 ..............................2–3
FIGURE 2-2. REED-SOLOMON CODEC INSTALLATION................................................................................2–5
FIGURE 2-3. TURBO CODEC INSTALLATION..................................................................................................2–7
FOR RIBBON-CONFIGURED CONNECTOR FIGURE 2-4. DATA I/O CONNECTOR (J8)
REMOVAL/INSTALLATION.........................................................................................................................2–9
FIGURE 2-5. MAIN BOARD FIELD-CHANGEABLE CHIPS (SHOWN WITH OVERHEAD CARD
REMOVED) ...................................................................................................................................................2–10
FIGURE 3-1. REAR PANEL ...................................................................................................................................3–1
FIGURE 4-1. FRONT PANEL VIEW .....................................................................................................................4–1
FIGURE 4-2. KEYPAD ...........................................................................................................................................4–3
FIGURE 4-3. MENU TREE.....................................................................................................................................4–6
FIGURE 4-4. RF LOOPBACK ..............................................................................................................................4–21
FIGURE 4-5. IF LOOPBACK ...............................................................................................................................4–22
FIGURE 4-6. BASEBAND LOOPBACK..............................................................................................................4–30
FIGURE 4-7. INTERFACE LOOPBACK .............................................................................................................4–31
FIGURE 6-1. EIA-422, EIA-232, OR V.35 MASTER/MASTER CLOCKING DIAGRAM..................................6–3
FIGURE 6-2. EIA-422, EIA-232, OR V.35 MASTER/SLAVE CLOCKING DIAGRAM.....................................6–4
FIGURE 6-3. CLOCK SLIP ..................................................................................................................................6–5
FIGURE 6-4. DOPPLER SHIFT..............................................................................................................................6–6
FIGURE 7-1. VITERBI DECODER........................................................................................................................7–7
FIGURE 7-2. VITERBI DECODER AND REED-SOLOMON ..............................................................................7–8
FIGURE 7-3. BPSK AND {O}QPSK BER PERFORMANCE ...............................................................................7–9
FIGURE 7-4. TURBO PRODUCT CODEC..........................................................................................................7–10
FIGURE 7-5. SEQUENTIAL DECODER, REED-SOLOMON, AND 1544 KBPS .............................................7–11
FIGURE 7-6. SEQUENTIAL DECODER AND 56 KBPS ...................................................................................7–12
FIGURE 7-7. SEQUENTIAL DECODER AND 1544 KBPS................................................................................7–13
FIGURE 8-1. FAULT ISOLATION TEST SETUP.................................................................................................8–2
FIGURE 8-2. TYPICAL OUTPUT SPECTRUM ...................................................................................................8–5
FIGURE 8-3. TYPICAL EYE CONSTELLATIONS ..............................................................................................8–6
FIGURE 10-1. AUPC BLOCK DIAGRAM ..........................................................................................................10–2
FIGURE 11-1. TRANSMIT SECTION OF THE ASYMMETRICAL LOOP TIMING BLOCK DIAGRAM.....11–2
FIGURE 11-2. RECEIVE SECTION OF THE ASYMMETRICAL LOOP TIMING BLOCK DIAGRAM ........11–3
FIGURE 14-1. SEQUENTIAL DECODER BLOCK DIAGRAM.........................................................................14–1
FIGURE 14-2. VITERBI DECODER BLOCK DIAGRAM..................................................................................14–3
FIGURE 15-1. REED-SOLOMON PCB (AS/5304-1)...........................................................................................15–1
FIGURE 15-2.REED-SOLOMON CODEC BLOCK DIAGRAM .........................................................................15–2
FIGURE 15-3. REED-SOLOMON ENCODER SECTION BLOCK DIAGRAM ................................................15–3
FIGURE 15-4. REED-SOLOMON CODE PAGE FORMAT ................................................................................15–4
FIGURE 15-5. REED-SOLOMON DECODER SECTION BLOCK DIAGRAM ................................................15–5
FIGURE A-1. CARRIER LEVEL VS SYMBOL RATE......................................................................................A–18
FIGURE C-1. SNM-1001L BURST MODE FAULT TREE ................................................................................ C–13