Table 5-2. axi monitor bfm configuration – Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite User Manual
Page 93
SystemVerilog Monitor BFM
Monitor BFM Configuration
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
93
April 2014
A monitor BFM has configuration fields that you can set via the
configure variables such as timeout factors and setup and hold times. You can also get the value
of a configuration field via the
function.
describes the full list of
configuration fields.
AXI4_RDATA_WIDTH
Read data signal width in bits. This applies to the
RDATA signals. Refer to the AMBA AXI Protocol
Specification for more details. Default: 64.
AXI4_WDATA_WIDTH
Write data signal width in bits. This applies to the
WDATA signals. Refer to the AMBA AXI Protocol
Specification for more details. Default: 64.
index
Ignored for the SystemVerilog monitor BFM.
READ_ACCEPTANCE_
CAPABILITY
The maximum number of outstanding read transactions
that can be accepted by the monitor BFM. This parameter
is set with the Qsys Parameter Editor. See “
Default: 16.
WRITE_ACCEPTANCE_
CAPABILITY
The maximum number of outstanding write transactions
that can be accepted by the monitor BFM. This parameter
is set with the Qsys Parameter Editor. See “
Default: 16.
COMBINED_ACCEPTANCE_
CAPABILITY
The maximum number of outstanding combined read and
write transactions that can be accepted by the monitor
BFM. This parameter is set with the Qsys Parameter
Editor. See “
details.
Default: 16.
Table 5-2. AXI Monitor BFM Configuration
Configuration Field
Description
Timing Variables
AXI4_CONFIG_SETUP_TIME
The setup time prior to the active edge
of ACLK, in units of simulator time-
steps for all signals.
1
Default: 0.
AXI4_CONFIG_HOLD_TIME
The hold time after the active edge of
ACLK, in units of simulator time-
steps for all signals.
1
Default: 0.
AXI4_CONFIG_MAX_TRANSACTION_
TIME_FACTOR
The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
Table 5-1. AXI Monitor BFM Signal Width Parameters (cont.)