Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite User Manual

Mentor, Verification ip altera edition amba axi4-lite, User guide

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Mentor

Verification IP Altera Edition

AMBA AXI4-Lite

User Guide

Software Version 10.3

April 2014

This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this
document may duplicate this document in whole or in part for internal business purposes only, provided that this entire
notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable
effort to prevent the unauthorized use and distribution of the proprietary information.

Table of contents

Document Outline

Table of Contents
List of Examples
List of Figures
List of Tables
Preface
- About This User Guide
- AMBA AXI Protocol Specification
- Protocol Restrictions
  - BFM Dependencies Between Handshake Signals
- Mentor VIP AE License Requirements
- Supported Simulators
- Simulator GCC Requirements
Chapter 1 Mentor VIP Altera Edition
- Advantages of Using BFMs and Monitors
- Implementation of BFMs
- What Is a Transaction?
- AXI4-Lite Transactions
  - AXI4-Lite Write Transaction Master and Slave Roles
  - AXI Read Transaction Master and Slave Roles
Chapter 2 SystemVerilog API Overview
- Configuration
  - set_config()
  - get_config()
- Creating Transactions
  - Transaction Record
    - AXI4-Lite Transaction Definition
  - create*_transaction()
- Executing Transactions
  - execute_transaction(), execute*_phase()
- Waiting Events
  - wait_on()
  - get*_transaction(), get*_phase(), get*_cycle()
- Access Transaction Record
  - set*()
  - get*()
- Operational Transaction Fields
Chapter 3 SystemVerilog Master BFM
- Master BFM Protocol Support
- Master Timing and Events
- Master BFM Configuration
- Master Assertions
  - Assertion Configuration
- SystemVerilog Master API
Chapter 4 SystemVerilog Slave BFM
- Slave BFM Protocol Support
- Slave Timing and Events
- Slave BFM Configuration
- Slave Assertions
  - Assertion Configuration
- SystemVerilog Slave API
- Helper Functions
Chapter 5 SystemVerilog Monitor BFM
- Inline Monitor Connection
- Monitor BFM Protocol Support
- Monitor Timing and Events
- Monitor BFM Configuration
- Monitor Assertions
  - Assertion Configuration
- SystemVerilog Monitor API
- Helper Functions
Chapter 6 SystemVerilog Tutorials
- Verifying a Slave DUT
  - BFM Master Test Program
- Verifying a Master DUT
  - BFM Slave Test Program
Chapter 7 VHDL API Overview
- Configuration
  - set_config()
  - get_config()
- Creating Transactions
  - Transaction Record
    - Transaction Definition
  - create*_transaction()
- Executing Transactions
  - execute_transaction(), execute*_phase()
- Waiting Events
  - wait_on()
  - get*_transaction(), get*_phase(), get*_cycle()
- Access Transaction Record
  - set*()
  - get*()
- Operational Transaction Fields
Chapter 8 VHDL Master BFM
- Overloaded Procedure Common Arguments
- Master BFM Protocol Support
- Master Timing and Events
- Master BFM Configuration
- Master Assertions
  - Assertion Configuration
- VHDL Master API
Chapter 9 VHDL Slave BFM
- Slave BFM Protocol Support
- Slave Timing and Events
- Slave BFM Configuration
- Slave Assertions
  - Assertion Configuration
- VHDL Slave API
- Helper Functions
Chapter 10 VHDL Monitor BFM
- Inline Monitor Connection
- Monitor BFM Protocol Support
- Monitor Timing and Events
- Monitor BFM Configuration
- Monitor Assertions
  - Assertion Configuration
- VHDL Monitor API
Chapter 11 VHDL Tutorials
- Verifying a Slave DUT
  - BFM Master Test Program
- Verifying a Master DUT
  - BFM Slave Test Program
Chapter 12 Getting Started with Qsys and the BFMs
- Setting Up Simulation from a UNIX Platform
- Setting Up Simulation from the Windows GUI
  - Running the Qsys Tool
  - Running a Simulation
Appendix A
- AXI4-Lite Assertions
Appendix B SystemVerilog Test Programs
- SystemVerilog AXI4-Lite Master BFM Test Program
- SystemVerilog AXI4-Lite Slave BFM Test Program
Appendix C VHDL Test Programs
- AXI4-Lite VHDL Master BFM Test Program
- AXI4-Lite VHDL Slave BFM Test Program
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