Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 25)

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AXI4-Lite Transactions
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 25
April 2014
Figure 1-3. Slave Write Transaction Phases
The slave then executes a write response phase by calling the execute_write_response_phase()
task and completes its role in the write transaction.
AXI Read Transaction Master and Slave Roles
Note
The following description of a read transaction references the SystemVerilog BFM API
tasks. There are equivalent VHDL BFM API procedures that perform the same
functionality.
A read transaction is similar to a write transaction. The master initiates the read by calling the
create_read_transaction() and execute_transaction() tasks. The execute_transaction() calls the
the execute_read_addr_phase() task followed by the get_read_data_phase() task as illustrated
in Figure 1-4 .
Master
interface Slave
interface
Write
data
Write response channel
Write data channel
Write address channel
Write
response
Address
and
control
execute_write_response_phase() - Slave
get_write_data_phase() - Slave
get_write_addr_phase() - Slave