Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 67)

SystemVerilog Slave BFM
Slave Assertions
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 67
April 2014
1.
Refer to Slave Timing and Events for details of simulator time-steps.
Slave Assertions
Each slave BFM performs protocol error checking using the built-in assertions.
Note
The built-in BFM assertions are independent of programming language and simulator.
Assertion Configuration
By default, all built-in assertions are enabled in the slave AXI4-Lite BFM. To globally disable
them in the slave BFM, use the
set_config() command as the following example illustrates:
set_config(AXI4_CONFIG_ENABLE_ALL_ASSERTIONS,0)
Alternatively, you can disable individual built-in assertions by using a sequence of get_config()
and set_config() commands on the respective assertion. For example, to disable assertion
checking for the AWADDR signal changing between the AWVALID and AWREADY
handshake signals, use the following sequence of commands:
// Define a local bit vector to hold the value of the assertion bit vector
bit [255:0] config_assert_bitvector;
AXI4_CONFIG_NUM_OUTSTANDING_
WR_PHASE Holds the number of outstanding write
phases from the master that can be
processed by the slave.
Default = 0.
AXI4_CONFIG_NUM_OUTSTANDING_
RD_PHASE Holds the number of outstanding read
phases to the master that can be
processed by the slave.
Default = 0.
Error Detection
AXI4_CONFIG_ENABLE_ALL_
ASSERTIONS Global enable/disable of all assertion
checks in the BFM.
0 = disabled
1 = enabled (default)
AXI4_CONFIG_ENABLE_ASSERTION Individual enable/disable of assertion
check in the BFM.
0 = disabled
1 = enabled (default)
Table 4-2. Slave BFM Configuration (cont.)
Configuration Field Description