Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 337)

VHDL Tutorials
Verifying a Slave DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 337
April 2014
Example 11-2. m_rd_data_phase_ready_delay
-- Variable : m_rd_data_phase_ready_delay
signal m_rd_data_phase_ready_delay : integer := 2;
Configuration and Initialization
The master test process creates and executes read and write transactions. The whole process
runs concurrently with other processes in the test program, using the path_id = AXI4_PATH_0.
See “
Overloaded Procedure Common Arguments ” on page 151 for details of path_id.
The process waits for the ARESETn signal to be deasserted, followed by a positive ACLK edge,
as shown in
Example 11-3 . This satisfies the protocol requirements in Section A3.1.2 of the
AXI Protocol Specification.
Example 11-3. Configuration and Initialization
-- Master test
process
variable tr_id: integer;
variable data_words : std_logic_vector(AXI4_MAX_BIT_SIZE-1 downto 0);
variable lp: line;
begin
wait_on(AXI4_RESET_0_TO_1, index, axi4_tr_if_0(index));
wait_on(AXI4_CLOCK_POSEDGE, index, axi4_tr_if_0(index));
Create and Execute Write Transactions
To generate AXI4-Lite protocol traffic, the master test program must create a transaction before
executing it. The code shown in
Example 11-4 calls the create_write_transaction() procedure,
providing only the start address argument of the transaction.
This example has an AXI4-Lite write data bus width of 32 bits; therefore, a single beat of data
conveys 4 bytes across the data bus. The call to the
set_data_words() procedure sets the first
element of the data_words transaction field with the value 1 on byte lane 1, with a result of
x”0000_0100”. However, the AXI4-Lite protocol permits narrow transfers with the use of the
write strobes signal WSTRB to indicate which byte lane contains valid write data, and therefore
indicates to the slave DUT which data byte lane will be written into memory. The write strobes
WSTRB signal indicates to the slave which byte lane contains valid write data to be written to
the slave memory. Similarly, you can call the
set_write_strobes() procedure to set the first
element of the write_strobes transaction field with the value 2, indicating that only byte lane 1
contains valid data. Calling the
execute_transaction() procedure executes the transaction on the
protocol signals.
All other transaction fields default to legal protocol values (see create_write_transaction()
procedure for details).