Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 121)

SystemVerilog Tutorials
Verifying a Slave DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 121
April 2014
handle_write_resp_ready()
The handle_write_resp_ready() task handles the BREADY signal for the write response
channel. In a forever loop, it delays the assertion of the BREADY signal based on the settings of
the
master_ready_delay_mode and m_wr_resp_phase_ready_delay as shown in Example 6-7 .
If the master_delay_ready_mode = AXI4_VALID2READY, then the BREADY signal is
immediately deasserted using the nonblocking call to the
execute_write_resp_ready() task and
waits for a write channel response phase to occur with a call to the blocking
get_write_response_cycle() task. A received write response phase indicates that the BVALID
signal has been asserted, triggering the starting point for the delay of the BREADY signal by the
number of ACLK cycles defined by
m_wr_resp_phase_ready_delay . After the delay, another
call to the execute_write_resp_ready() task to assert the BREADY signal completes the
BREADY handling. The seen_valid_ready flag is set to indicate the end of a response phase
when both BVALID and BREADY are asserted, and the completion of the write transaction.
If the master_delay_ready_mode = AXI4_TRANS2READY, then a check of the
seen_valid_ready flag is performed to indicate that a previous write transaction has completed.
If a write transaction is still active (indicated by either BVALID or BREADY not asserted),
then the code waits until the previous write transaction has completed. The BREADY signal is
deasserted using the nonblocking call to the
execute_write_resp_ready() task and waits for the
number of ACLK cycles defined by m_wr_resp_phase_ready_delay . A nonblocking call to the
execute_write_resp_ready() task to assert the BREADY signal completes the BREADY
handling. The seen_valid_ready flag is cleared to indicate that only BREADY has been
asserted.