Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 349)

VHDL Tutorials
Verifying a Master DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 349
April 2014
Example 11-16. handle_write
-- handle_write : write data phase through path 1
-- This method receive write data phase for write transaction
process
variable write_trans: integer;
variable byte_length : integer;
variable addr : std_logic_vector(AXI4_MAX_BIT_SIZE-1 downto 0);
variable data : std_logic_vector(7 downto 0);
variable last : integer := 0;
begin
loop
pop_transaction_id(write_trans, AXI4_QUEUE_ID_0, index, AXI4_PATH_1,
axi4_tr_if_1(index));
get_write_data_phase(write_trans, 0, last, index, AXI4_PATH_1,
axi4_tr_if_1(index));
get_write_addr_data(write_trans, 0, 0, byte_length, addr, data,
index, AXI4_PATH_1, axi4_tr_if_1(index));
do_byte_write(addr, data);
if byte_length > 1 then
for j in 1 to byte_length-1 loop
get_write_addr_data(write_trans, 0, j, byte_length, addr, data,
index, AXI4_PATH_1, axi4_tr_if_1(index));
do_byte_write(addr, data);
end loop;
end if;
push_transaction_id(write_trans, AXI4_QUEUE_ID_2, index,
AXI4_PATH_1, axi4_tr_if_1(index));
end loop;
wait;
end process;
handle_response
The handle_response process sends a response back to the master to complete a write
transaction. It uses unique path and queue identifiers to work concurrently with other processes.
In a loop, the pop_transaction_id() procedure call returns the transaction_id from the queue for
the slave BFM, indexed by the index argument, as shown in Example 11-17 . A write_trans
variable is previously defined to hold the transaction_id. If the queue is empty, then
push_transaction_id() will block until content is available.
The call to set_wr_resp_valid_delay() sets the BVALID signal delay for the response prior to
calling execute_write_response_phase() to execute the response over the protocol signals.