Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 338)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 338
VHDL Tutorials
Verifying a Slave DUT
April 2014
Example 11-4. Create and Execute Write Transactions
-- 4 x Writes
-- Write data value 1 on byte lanes 1 to address 1.
create_write_transaction(1, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"00000100";
set_data_words(data_words, tr_id, index, axi4_tr_if_0(index));
set_write_strobes(2, tr_id, index, axi4_tr_if_0(index));
report "master_test_program: Writing data (1) to address (1)";
-- By default it will run in Blocking mode
execute_transaction(tr_id, index, axi4_tr_if_0(index));
In the master test program, three subsequent write transactions are created and executed in a
similar manner to
Example 11-4 . See the “ AXI4-Lite VHDL Master BFM Test Program ” on
page 397for details.
Create and Execute Read Transactions
The code excerpt in Example 11-5 reads the data that has been previously written into the slave
memory. The master test program first creates a read transaction by calling the
create_read_transaction() procedure, providing only the start address argument.
The read transaction is then executed on the protocol signals by calling the
execute_transaction() procedure.
The read data is obtained using the get_data_words() procedure to get the data_words
transaction field value. The result of the read data is compared with the expected data, and a
message displays the transcript.
Example 11-5. Create and Execute Read Transactions
--4 x Reads
--Read data from address 1.
create_read_transaction(1, tr_id, index, axi4_tr_if_0(index));
execute_transaction(tr_id, index, axi4_tr_if_0(index));
get_data_words(data_words, tr_id, index, axi4_tr_if_0(index));
if(data_words(31 downto 0) = x"00000100") then
report "master_test_program: Read correct data (1) at address (1)";
else
hwrite(lp, data_words(31 downto 0));
report "master_test_program: Error: Expected data (1) at address 1, but
got " & lp.all;
end if;
In the master test program, three subsequent read transactions are created and executed in a
similar manner to
Example 11-5 . See “ AXI4-Lite VHDL Master BFM Test Program ” on
page 397 for details.