Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 396)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 396
SystemVerilog Test Programs
SystemVerilog AXI4-Lite Slave BFM Test Program
April 2014
join_none
bfm.get_write_data_cycle;
repeat(tmp_ready_delay - 1) bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.execute_write_data_ready(1'b1);
seen_valid_ready = 1'b1;
end
else // AXI4_TRANS2READY
begin
if (seen_valid_ready == 1'b0)
begin
do
bfm.wait_on(AXI4_CLOCK_POSEDGE);
while (!((bfm.WVALID === 1'b1) && (bfm.WREADY === 1'b1)));
end
fork
bfm.execute_write_data_ready(1'b0);
join_none
repeat(tmp_ready_delay) bfm.wait_on(AXI4_CLOCK_POSEDGE);
fork
bfm.execute_write_data_ready(1'b1);
join_none
seen_valid_ready = 1'b0;
end
end
endtask
endmodule