Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 336)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 336
VHDL Tutorials
Verifying a Slave DUT
April 2014
In this example, the master test program also compares the written data with that read back from
the slave DUT, reporting the result of the comparison.
A top-level file instantiates and connects all the components required to test and monitor the
DUT, and controls the system clock (ACLK) and reset (ARESETn) signals.
BFM Master Test Program
A master test program using the master BFM API is capable of creating a wide range of
stimulus scenarios to verify a slave DUT. However, this tutorial restricts the master BFM
stimulus to write transactions followed by read transactions to the same address, and then
compares the read data with the previously written data. For a complete code listing of this
master test program, refer to “
AXI4-Lite VHDL Master BFM Test Program ” on page 397.
The master test program contains the following:
•
A create_transactions process that creates and executes read and write transactions.
•
Processes handle_write_resp_ready and handle_read_data_ready to handle the write
response channel BREADY and read data channel RREADY signals, respectively.
•
Variables m_wr_resp_phase_ready_delay and m_rd_data_phase_ready_delay to set the
delay of the BREADY and RREADY signals.
The following sections describe the main processes and variables:
m_wr_resp_phase_ready_delay
The m_wr_resp_phase_ready_delay variable holds the BREADY signal delay. The delay value
extends the length of the write response phase by a number of ACLK cycles.
Example 11-1 below shows the AWREADY signal delayed by two ACLK cycles. You can edit
this variable to change the AWREADY signal delay.
Example 11-1. m_wr_resp_phase_ready_delay
-- Variable : m_wr_resp_phase_ready_delay
signal m_wr_resp_phase_ready_delay :integer := 2;
m_rd_data_phase_ready_delay
The m_rd_data_phase_ready_delay variable holds the RREADY signal delay. The delay value
extends the length of each read data phase (beat) by a number of ACLK cycles.
Example 11-2 below shows the RREADY signal delayed by two ACLK cycles. You can edit
this variable to change the RREADY signal delay.