Table 3-2. master bfm configuration – Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite User Manual
Page 41
SystemVerilog Master BFM
Master BFM Configuration
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
41
April 2014
A master BFM has configuration fields that you can set with the
configure timeout factors, and setup and hold times, and so on. You can also get the value of a
configuration field using the
describes the full list of
configuration fields.
WRITE_ISSUING_
CAPABILITY
The maximum number of outstanding write transactions that
can be issued from the master BFM. This parameter is set
with the Qsys Parameter Editor. See “
Default: 16.
COMBINED_ISSUING_
CAPABILITY
The maximum number of outstanding combined read and
write transactions that can be issued from the master BFM.
This parameter is set with the Qsys Parameter Editor. See
“
Default: 16.
Table 3-2. Master BFM Configuration
Configuration Field
Description
Timing Variables
AXI4_CONFIG_SETUP_TIME
The setup-time prior to the active edge
of ACLK, in units of simulator time-
steps for all signals.1 Default: 0.
AXI4_CONFIG_HOLD_TIME
The hold-time after the active edge of
ACLK, in units of simulator time-steps
for all signals.1 Default: 0.
AXI4_CONFIG_MAX_TRANSACTION_TIME_
FACTOR
The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
AXI4_CONFIG_BURST_TIMEOUT_FACTOR
The maximum delay between the
individual phases of a read/write
transaction in clock cycles. Default:
10000.
AXI4_CONFIG_MAX_LATENCY_AWVALID_
ASSERTION_TO_AWREADY
The maximum timeout duration from
the assertion of AWVALID to the
assertion of AWREADY in clock
periods. Default: 1000.
AXI4_CONFIG_MAX_LATENCY_ARVALID_
ASSERTION_TO_ARREADY
The maximum timeout duration from
the assertion of ARVALID to the
assertion of ARREADY in clock
periods. Default: 10000.
Table 3-1. Master BFM Signal Width Parameters (cont.)
Signal Width Parameter
Description