Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 282)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 282
VHDL Monitor BFM
Monitor Assertions
April 2014
1.
Refer to Monitor Timing and Events for details of simulator time-steps.
Monitor Assertions
The monitor BFM performs protocol error checking via built-in assertions.
Note
The built-in BFM assertions are independent of programming language and simulator.
AXI4_CONFIG_MAX_LATENCY_BVALID_
ASSERTION_TO_BREADY The maximum timeout duration from the
assertion of BVALID to the assertion of
BREADY in clock periods. Default:
10000.
AXI4_CONFIG_MAX_LATENCY_WVALID_
ASSERTION_TO_WREADY The maximum timeout duration from the
assertion of WVALID to the assertion of
WREADY in clock periods. Default:
10000.
Slave Attributes
AXI4_CONFIG_SLAVE_START_ADDR Configures the start address map for the
slave.
AXI4_CONFIG_SLAVE_END_ADDR Configures the end address map for the
slave.
Monitor Attributes
AXI4_CONFIG_AXI4LITE_axi4 Configures the AXI4 monitor BFM to be
AXI4-Lite compatible.
0 = disabled (default)
1 = enabled
Error Detection
AXI4_CONFIG_ENABLE_ALL_ASSERTIONS Global enable/disable of all assertion
checks in the BFM.
0 = disabled
1 = enabled (default)
AXI4_CONFIG_ENABLE_ASSERTION Individual enable/disable of assertion
check in the BFM.
0 = disabled
1 = enabled (default)
Table 10-2. Monitor BFM Configuration (cont.)
Configuration Field Description