Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 63)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 63
April 2014
Chapter 4
SystemVerilog Slave BFM
This chapter describes the SystemVerilog slave BFM. Each BFM has an API that contains tasks
and functions to configure the BFM and to access the dynamic
Transaction Record during the
lifetime of the transaction.
Slave BFM Protocol Support
This section defines protocol support for various AXI BFMs. The AXI4-Lite slave BFM
supports the AMBA AXI4-Lite protocol with restrictions described in “
Protocol Restrictions ”
on page 17.
Slave Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA AXI
Protocol Specification chapter, which you can use to reference details of the following slave
BFM API timing and events.
The specification does not define any timescale or clock period with signal events sampled and
driven at rising ACLK edges. Therefore, the slave BFM does not contain any timescale,
timeunit, or timeprecision declarations with the signal setup and hold times specified in units of
simulator time-steps.
The simulator time-step resolves to the smallest of all the time-precision declarations in the test
bench and design IP based on using the directives, declarations, options, and initialization files
below:
•
` timescale directives in design elements
•
Timeprecision declarations in design elements
•
Compiler command-line options
•
Simulation command-line options
•
Local or site-wide simulator initialization files
If there is no timescale directive, the default time unit and time precision are tool specific. Using
timeunit and timeprecision declarations are recommended. Refer to the IEEE Standard for
SystemVerilog, Section 3.14 for details.