Channel handshake delay, Handshake delay – Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite User Manual
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Mentor Verification IP AE AXI4-Lite User Guide, V10.3
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SystemVerilog API Overview
Operational Transaction Fields
April 2014
You can configure this behavior to be nonblocking by setting the operation_mode transaction
field to the enumerate type value AXI4_TRANSACTION_NON_BLOCKING instead of the
default AXI4_TRANSACTION_BLOCKING.
For example, in a master BFM test program you create a transaction by calling the
tasks, which creates a transaction
record. Before executing the transaction record, you can change the operation_mode as follows:
// Create a write transaction to create a transaction record
trans = bfm.create_write_transaction(1);
// Change operation_mode to be nonblocking in the transaction record
trans.operation_mode(AXI4_TRANSACTION_NON_BLOCKING);
Channel Handshake Delay
Each of the five protocol channels have *VALID and *READY handshake signals that control
the rate at which information is transferred between a master and slave. Refer to the
for details of the AXI4-Lite BFM API.
Handshake Delay
The delay between the *VALID and *READY handshake signals for each of the five protocol
channels is controlled in a BFM test program using execute_*_ready(), get_*_ready(), and
get_*_cycle() tasks. The execute_*_ready() tasks place a value onto the *READY signals and
the get_*_ready() tasks retrieve a value from the *READY signals. The get_*_cycle() tasks
wait for a *VALID signal to be asserted and are used to insert a delay between the *VALID and
*READY signals in the BFM test program.
For example, the master BFM test program code below inserts a specified delay between the
read channel RVALID and RREADY handshake signals using the execute_read_data_ready()
and get_read_data_cycle() tasks.
// Set the RREADY signal to ‘0’ so that it is nonblocking
fork
bfm.execute_read_data_ready(1'b0);
join_none
// Wait until the RVALID signal is asserted and then wait_on the specified
// number of ACLK cycles
bfm.get_read_data_cycle;
repeat(5) bfm.wait_on(AXI4_CLOCK_POSEDGE);
// Set the RREADY signal to ‘1’ so that it blocks for an ACLK cycle
bfm.execute_read_data_ready(1'b1);