Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 125)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 125
April 2014
Example 6-9. do_byte_read()
// Function : do_byte_read
// Function to provide read data byte from memory at
// particular input address
function bit[7:0] do_byte_read(addr_t addr);
return mem[addr];
endfunction
do_byte_write()
The do_byte_write() function, when called, writes a data byte to the Internal Memory mem,
given an address location as shown below.
You can edit this function to modify the way the write data is stored in the internal memory.
Example 6-10. do_byte_write()
// Function : do_byte_write
// Function to write data byte to memory at particular
// input address
function void do_byte_write(addr_t addr, bit [7:0] data);
mem[addr] = data;
endfunction
m_rd_addr_phase_ready_delay
The m_rd_addr_phase_ready_delay variable holds the ARREADY signal delay. The delay
value extends the length of the read address phase by a number of ACLK cycles. The starting
point of the delay is determined by the
slave_ready_delay_mode variable configuration.
Example 6-11 shows the ARREADY signal delayed by two ACLK cycles. You can edit this
variable to change the ARREADY signal delay.
Example 6-11. m_rd_addr_phase_ready_delay
// Variable : m_rd_addr_phase_ready_delay
int m_rd_addr_phase_ready_delay = 2;
m_wr_addr_phase_ready_delay
The m_wr_addr_phase_ready_delay variable holds the AWREADY signal delay. The delay
value extends the length of the write address phase by a number of ACLK cycles. The starting
point of the delay is determined by the
slave_ready_delay_mode variable configuration.
Example 6-12 shows the AWREADY signal delayed by two ACLK cycles. You can edit this
variable to change the AWREADY signal delay.