Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 37)

SystemVerilog API Overview
Operational Transaction Fields
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 37
April 2014
VALID Signal Delay Transaction Fields
The transaction record contains a *_valid_delay transaction field for each of the five protocol
channels to configure the delay value prior to the assertion of the *VALID signal for the
channel. The master BFM holds the delay configuration for the *VALID signals that it asserts,
and the slave BFM holds the delay configuration for the *VALID signals that it asserts.
Table 2-2 specifies which *_valid_delay fields are configured by the master and slave BFMs.
*READY Handshake Signal Delay Transaction Fields
The transaction record contains a *_ready_delay transaction field for each of the five protocol
channels to store the delay value that occurred between the assertion of the *VALID and
*READY handshake signals for the channel.
Table 2-3 specifies the *_ready_delay field
corresponding to the *READY signal delay.
Transaction Done
The transaction_done field in each transaction indicates when the transaction is complete.
In a master BFM test program, you call the get_read_data_phase() task to investigate whether a
read transaction is complete, and the get_write_response_phase() to investigate whether a write
transaction is complete.
Table 2-2. Master and Slave *_valid_delay Configuration Fields
Signal Operational Transaction Field Configuration BFM
AWVALID address_valid_delay Master
WVALID data_valid_delay Master
BVALID write_response_valid_delay Slave
ARVALID address_valid_delay Master
RVALID data_valid_delay Slave
Table 2-3. Master and Slave *_ready_delay Transaction Fields
Signal Operational Transaction Field
AWREADY address_ready_delay
WREADY data_ready_delay
BREADY write_response_ready_delay
ARREADY address_ready_delay
RREADY data_ready_delay