Multiplier control register 0 (mcnt0) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 76
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
76
Multiplier Control Register 0 (MCNT0)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
LRSFT
Bit 7
CSE
Bit 6
SCE
Bit 5
MAS4–0
Bits 4–0
Left/right shift. The LRSFT bit is cleared to 0 following either a system reset or the initialization of the
accelerator. The LRSFT bit is programmed to 0 when a left shift is required and is programmed to 1 for
a right shift. LRSFT does not alter any other type of calculation other than the shift function.
Circular shift enable. The CSE bit is cleared to 0 following a system reset. When CSE and SCE are
cleared to 0’s, all left or right shifts performed on the MA register, as per the programming of LRST and
MAS4–MAS0, shift clear bit values into the most significant bit for a right shift and the least significant
bit for a left shift. The least significant bit is also lost when doing a right shift, and the most significant bit
is lost when doing a left shift. When CSE is set to 1 and SCE is cleared to 0, the most significant bit of
the MA register is shifted into the least most significant bit for a left shift. Similarly, the least significant
bit of the MA register is shifted into the most significant bit for a right shift. When CSE is cleared to 0 and
SCE is set to 1, the shift carry bit is shifted into the most significant bit for the right shift and the least
significant bit for a left shift. The least significant bit is also lost when doing a right shift, and the most
significant bit is lost when doing a left shift. When CSE and SCE are set to 1, the most significant MA bit
is shifted into the shift carry bit. The shift carry bit is shifted into the least significant MA bit when doing
a left shift. The least significant MA bit is shifted into the shift carry bit, while the shift carry bit is shifted
into the most significant MA bit when doing a right shift.
Shift carry enable. The SCE bit is cleared to 0 following a system reset. When SCE is cleared to a 0, all
left or right shifts performed on the MA register, as per the programming of CSE, LRST, and MAS4–MAS0,
do not incorporate the shift carry bit SCB (MCNT1.5) as a part of the shifting process. When SCE is set
to a 1, the shift carry bit is shifted into the least significant bit for a left shift and into the most significant
bit for a right shift. If CSE is cleared to a 0, the shift carry bit remains unchanged during the shift process.
If CSE is set to a 1, the most significant MA bit is shifted into the shift carry bit when doing a left shift,
and least most significant MA bit is shifted into the shift carry bit when doing a right shift.
Multiplier register shift bits. These bits determine the number of shifts performed when a shift opera-
tion is performed with the arithmetic accelerator and are also used to indicate how many shifts were per-
formed during a previous normalization operation. These bits are cleared to 00000b following a system
reset or the initialization of the arithmetic accelerator.
When these bits are cleared to 00000b after loading the arithmetic accelerator, the device normalizes
the 32-bit value loaded into the arithmetic accelerator accumulator rather than shifting it. Following the
normalization operation, the MAS4–0 bits are modified to indicate how many shifts were performed.
MAS4
MAS3 MAS2
MAS1
MAS0
NUMBER OF
SHIFTS OF
ARITHMETIC
ACCELERATOR
ACCUMULATOR
0
0
0
0
0
Normalization
0
0
0
0
1
Shift by 1
0
0
0
1
0
Shift by 2
0
0
0
1
1
Shift by 3
—
—
—
—
—
—
1
1
1
1
0
Shift by 30
1
1
1
1
1
Shift by 31
7
6
5
4
3
2
1
0
SFR D1h
LRSFT
CSE
SCE
MAS4
MAS3
MAS2
MAS1
MAS0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
Maxim Integrated