Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual

Page 69

High-Speed Microcontroller User’s

Guide: Network Microcontroller

Supplement

SWB
Bit 5

CTM
Bit 4

4X/

Bit 3

ALEOFF
Bit 2

Bits 1-0

Switchback enable. When set to 1, SWB allows mask-enabled external interrupts, as well as enabled
serial port receive functions, to force the clock divide control (CD1 and CD0) bits from 11b (1024 oscil-

lator cycles per machine cycle) to 10b (four oscillator cycles per machine cycle). When SWB is cleared

to 0, switchback mode is disabled. Switchback is supported only from the divide-by-1024 mode. The

first switchback condition is initiated by the detection of a low on INT0, INT1, INT3 or INT5, or high on

INT2 or INT4, when the respective pin has been program-enabled to issue an interrupt. Note that the

switchback interrupt relationship requires that the respective external interrupt source be allowed to

generate an interrupt as defined by the priority of the interrupt and the state of nested interrupts, before

the switchback actually occurs. The second switchback condition occurs when the serial port is

enabled to receive data and is found to have an active-low start bit on the receive input pin. Serial port

transmit activity also forces a switchback if the SWB is set. Note that the serial port activity, as related

to the switchback, is independent of the serial port interrupt relationship. The automatic switchback is

only enabled when the clock-divided control bits have established a divide-by-1024 mode and the SWB

is set to 1.

Crystal multiplier enable. The CTM bit is used to enable the crystal clock multiplier. The CTM bit can
be changed only when the CD1 and CD0 bits are set to divide-by-4 mode and the RGMD is cleared to

0. When programmed to 0, the CTM bit disables the crystal clock multiplier to save energy and, when

programmed to 1, the CTM bit enables the crystal clock multiplier. The crystal clock multiplier requires

a startup stabilization period. Setting CTM to 1 from a previous 0 automatically clears the CKRY bit in

the EXIF register and starts the crystal clock warmup period. During the startup count, the CKRY bit

remains cleared and the CD1: 0 bits should not be changed to select the crystal clock multiplier until

the CKRY has indicated the startup time has elapsed (CKRY = 1). CTM cannot be changed from a 1 to

a 0 while the crystal clock multiplier option is selected by the CD1 and CD0 clock control bits. Setting

the CTM bit enables the crystal clock multiplier to run at the programmed 2X or 4X multiply rate estab-

lished by the 4X/2X bit. The 4X/2X bit cannot be altered unless the CTM bit is cleared. The CTM is also

automatically cleared to logic 0 when the processor enters into a stop mode.

System clock multiplier. The 4X/2X bit establishes the multiplication factor associated with the internal
crystal oscillator multiplier. Clearing this bit to a logic 0 sets the multiply function as a frequency doubler

(2X crystal frequency). Setting this bit to a logic 1 adjusts the multiply function to operate as a frequen-

cy quadrupler (4X crystal frequency). This bit must be established for the preferred multiplication factor

before setting the crystal multiplier (CTM) bit. The 4X/2X bit can only be altered when the CTM bit is

cleared. This prevents the system from changing the multiplication factor while the clock multiplier is

enabled and forces such a change to be made from the divide-by-4 mode.

ALE disable. When set to 1, this bit disables ALE (set high externally) during all on-board program and
data memory access times. External multiplexed address/data (off-chip) memory access (MUX = 0)

automatically enables ALE, independent of ALEOFF. External demultiplexed address/data (off-chip)

memory access (MUX = 1) automatically disables ALE if ALEOFF = 1 or leaves ALE toggling if ALEOFF

= 0. When ALEOFF is cleared to 0, ALE toggles normally at all times.

Reserved.

Maxim Integrated