Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 73)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
73
Timer 2 Mode (T2MOD)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
7 6 5 4 3 2 1 0
SFR C9h — — — D13T1 D13T2 — T2OE DCEN
RW-1 RW-1 RW-1 RW-0 RW-0 RW-1 RW-0 RW-0
Timer 2 Capture LSB (RCAP2L)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Timer 2 Capture MSB (RCAP2H)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Bits 7-5
D13T1
Bit 4
D13T2
Bit 3
Bit 2
T2OE
Bit 1
DCEN
Bit 0
Reserved.
Divide-by-13 clock option for timer 1. The D13T1 bit provides an alternate clock source to the timer 1
in place of the normal external T1 input pin. When D13T1 is cleared to 0, the clock source for timer 1 is
supplied through the standard T1 external input pin, the divide-by-12 of the oscillator (T1M = 0), or the
divide-by-4 of the oscillator (T1M = 1), as controlled by T1M and C/T. When D13T1 is set to a 1, the clock
source for timer 1 is supplied through a separate divide-by-13 of the system clock, independent of T1M.
The C/T bit must also be programmed to a 1 to select the divide-by-13 counter.
Divide-by-13 clock option for timer 2. The D13T2 bit provides an alternate clock source to the timer 2
in place of the normal external T2 input pin. When D13T2 is cleared to 0, the clock source for timer 2 is
supplied through the standard T2 external input pin, the divide-by-12 of the oscillator (T2M = 0), or the
divide-by-4 of the oscillator (T2M = 1), as controlled by T2M and C/T2. When D13T2 is set to a 1, the
clock source for timer 2 is supplied through a separate divide-by-13 of the system clock independent
of T2M. The C/T2 bit must also be programmed to a 1 to select the divide-by-13 counter.
Reserved.
Timer 2 output enable. Setting this bit to 1 enables the clock output function of T2 (P1.0) pin if C/T2 =
0. Timer 2 rollovers do not cause interrupts. Clearing this bit to 0 causes the T2 pin to function either as
a standard port pin or a counter input for timer 2.
Down-count enable. This bit, in conjunction with the T2EX pin, controls the direction that timer 2 counts
in 16-bit autoreload mode. Clearing this bit to 0 causes timer 2 to count up. Setting this bit to 1 causes
timer 2 to count up if the T2EX pin is 1, and timer 2 to count down if the T2EX pin is 0.
7 6 5 4 3 2 1 0
SFR CAh RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
7 6 5 4 3 2 1 0
SFR CBh RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
RCAP2L.7–0
Bits 7–0 Timer 2 capture LSB. This register is used to capture the TL2 value when timer 2 is configured in cap-
ture mode. RCAP2L is also used as the LSB of a 16-bit reload value when timer 2 is configured in autore-
load mode.
RCAP2H.7–0
Bits 7–0 Timer 2 capture MSB. This register is used to capture the TH2 value when timer 2 is configured in cap-
ture mode. RCAP2H is also used as the MSB of a 16-bit reload value when timer 2 is configured in
autoreload mode.
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