Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 178)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
178
DEFERRAL CHECK
When a transmit request is queued, the MAC monitors the CRS line to determine when the physical carrier becomes idle. If the phys-
ical carrier is not initially idle, the MAC defers transmission until the carrier becomes idle. The deferred state persists as long as the
physical carrier remains busy (CRS = 1). Optionally, the MAC can be configured to abort a transmit request if deferred excessively.
Setting the deferral check (DC) bit, bit 5 of the MAC control (00h) CSR register, forces the MAC to abort a transmit attempt that has
been deferred for more than 24,288 bit times. The deferral timer resets once the MAC is able to begin the transmit attempt. The defer-
ral (DFR) bit of the transmit status word is set if the MAC must defer during the transmit attempt. The excessive deferral (XDFR) bit of
the transmit status word is set if a packet is aborted because of excessive deferral.
DISABLE RETRY
Once transmission begins, the MAC monitors the COL pin to detect when a collision occurs. If a collision occurs within the first 512-
bit time normal collision window, the MAC sends a jamming signal and, by default, waits some random number of timeslots (accord-
ing to an internal back-off counter) before attempting the transmission again. The MAC attempts to transmit the packet as many as 16
times before aborting the transmit request because of excessive collisions. The MAC can optionally be configured to abort the trans-
mit packet if a collision occurs on the first attempt. The disable retry bit, bit 10 of the MAC control register, forces the MAC to abort the
packet if the COL pin is asserted (= 1) at any time during the transmission. The excessive collisions (XCOL) bit of the transmit status
word is set if the MAC aborts the transmit attempt because of excessive collisions (DTRY = 1 for 1 collision; DRTY = 0 for 16 collisions).
BACK-OFF LIMIT
Whenever a collision occurs during transmission, the MAC sends a jamming signal and backs off for some amount of time before
attempting the transmission again (given that DRTY = 0). An internal 10-bit pseudorandom counter is used to generate the back-off
delay. The back-off limit bits, BOLMT1:0, define how many bits of the counter are used in determining the back-off delay. The four set-
tings for the back-off delay counter are given in the DS80C400 data sheet.
LATE COLLISION CONTROL
The maximum round-trip network delay gives a 512-bit time window within which normal network collisions can be expected to occur.
By default, the DS80C400 MAC aborts a transmit packet if a collision is detected beyond this normal collision window. Optionally, the
MAC can be configured to react to a late collision in a similar fashion as it would to a normal collision. By setting the late-collision con-
trol (LCC) bit of the MAC control register, the MAC attempts retransmission of the packet just as if the collision had occurred within the
normal collision window. The observed late collision (OLTCOL) bit of the transmit status word is set when a collision is observed beyond
the normal 512-bit time collision window. The late collision (LTCOL) bit of the transmit status word is set if the transmit packet was abort-
ed because of a late collision.
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