Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 24)

Special-Function Registers
The DS80C400 has many unique features as compared to the standard 8052 microcontroller. These features are controlled by use of
the SFRs located in the unused locations of the 8052 SFR map. While maintaining complete instruction set compatibility with the 8052,
increased functionality is achieved with the DS80C400. The description for each bit indicates its read and write access, as well as its
reset state.
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
24
7 6 5 4 3 2 1 0
SFR 80h
P4.7
A19
P4.6
A18
P4.5
A17
P4.4
A16
P4.3
CE3
P4.2
CE2
P4.1
CE1
P4.0
CE0
RW-0 RW-0 RW-0 RW-0 RW-1 RW-1 RW-1 RW-1
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Port 4 (P4)
P4.7–0 Port 4 bit 7–0. This port is composed of eight pins that are user-programmable as I/O, extended program
memory chip enables, or extended address lines. The configuration of the eight pins is established
through the programming of the port 4 control register (P4CNT). Following a reset, and if EA is low,
P4.3–P4.1 are driven high and are assigned as chip enables; port pins P4.7–P4.4 and P4.0 are cleared
to a low state and are assigned as addresses and chip enable, respectively. Additional information on
external memory interfacing is found in the port 4 control register SFR description and later sections of
this user’s guide supplement.
Programmable parallel port. When programmed to function as a general I/O port (through the
P4CNT.7–P4CNT.0 in the port 4 control register), data written to the P4.7–P4.0 SFR bits results in setting
the port I/O configuration, as well as setting the state on the corresponding port pin. A 1 written to a port
4 latch, previously programmed low (0), activates a high-current, one-shot pullup on the corresponding
pin. This is followed by a static, low-current pullup, which remains on until the port is changed again.
The final high state of the port pin is considered a pseudo-input mode and can be easily overdriven from
an external source. Port latches previously in a high-output state do not change, nor does the high-cur-
rent one-shot fire when a 1 is loaded. Loading a 0 to a port latch results in a static, high-current pull-
down on the corresponding pin. This mode is termed the I/O output state, since no weak devices are
used to drive the pin. Port 4 pins, which have previously been assigned to function as an external mem-
ory interface (by the PCNT.7–PCNT.0 control bits), are not altered by a write to the port 4 SFR register.
Port 4 alternate function. Port 4 alternate function is established through the programming of the port
4 control register.
A19
Bit 7
A18
Bit 6
A17
Bit 5
A16
Bit 4
CE3
Bit 3
CE2
Bit 2
CE1
Bit 1
CE0
Bit 0
Program/data memory address 19. When this bit is set to logic 1 and the P4CNT register is configured
correctly, the corresponding device pin represents the A19 memory signal.
Program/data memory address 18. When this bit is set to logic 1 and the P4CNT register is configured
correctly, the corresponding device pin represents the A18 memory signal.
Program/data memory address 17. When this bit is set to logic 1 and the P4CNT register is configured
correctly, the corresponding device pin represents the A17 memory signal.
Program/data memory address 16. When this bit is set to logic 1 and the P4CNT register is configured
correctly, the corresponding device pin represents the A16 memory signal.
Program memory chip enable 3. When this bit is set to logic 1 and the P4CNT register is configured
correctly, the corresponding device pin represents the memory signal.
Program memory chip enable 2. When this bit is set to logic 1 and the P4CNT register is configured
correctly, the corresponding device pin represents the memory signal.
Program memory chip enable 1. When this bit is set to logic 1 and the P4CNT register is configured
correctly, the corresponding device pin represents the memory signal.
Program memory chip enable 0. When this bit is set to logic 1 and the P4CNT register is configured
correctly, the corresponding device pin represents the memory signal.
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