Stack pointer (sp), Data pointer low 0 (dpl), Data pointer high 0 (dph) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 25: Data pointer low 1 (dpl1), Data pointer high 1 (dph1)
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
25
SP.7–0
Bits 7–0
Stack pointer. This stack pointer identifies current location of the stack. The stack pointer is incre-
mented before every PUSH operation. This register defaults to 07h after reset. The reset value is used
when the stack is in 8051 stack mode. When the 10-bit stack is enabled (SA = 1), this register is com-
bined with the extended stack pointer (ESP: 9Bh) to form the 10-bit address.
DPL.7–0
Bits 7–0
Data pointer low 0. This register is the low byte of the standard 8051 data pointer and contains the low-
order byte of the 24-bit data address. The data pointer low byte 0 is cleared to 00h on all forms of reset.
DPH.7–0
Bits 7–0
Data pointer high 0. This register is the high byte of the standard 8051 data pointer and contains the
middle-order byte of the 24-bit data address. The data pointer high byte 0 is cleared to 00h on all forms
of reset.
DPL1.7–0
Bits 7–0
Data pointer low 1. This register is the low byte of auxiliary data pointer 1 and contains the low-order
byte of the 24-bit data address. When the SEL1: 0 bits (DPS.1:0) are set to 01b, DPX1, DPL1 and DPH1
are used during DPTR operations. The data pointer low byte 1 is cleared to 00h on all forms of reset.
DPH1.7–0
Bits 7–0
Data pointer high 1. This register is the high byte of auxiliary data pointer 1 and contains the middle-
order byte of the 24-bit data address. When the SEL1:0 bits (DPS1:0) are set to 01b, DPX1, DPL1 and
DPH1 are used during DPTR operations. The data pointer high byte 1 is cleared to 00h on all forms of
reset.
Data Pointer High 0 (DPH)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Stack Pointer (SP)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Data Pointer Low 0 (DPL)
7
6
5
4
3
2
1
0
SFR 81h
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-1
RW-1
RW-1
7
6
5
4
3
2
1
0
SFR 82h
DPL.7
DPL.6
DPL.5
DPL.4
DPL.3
DPL.2
DPL.1
DPL.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
7
6
5
4
3
2
1
0
SFR 83h
DPH.7
DPH.6
DPH.5
DPH.4
DPH.3
DPH.2
DPH.1
DPH.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Data Pointer High 1 (DPH1)
Data Pointer Low 1 (DPL1)
7
6
5
4
3
2
1
0
SFR 84h
DPL1.7
DPL1.6
DPL1.5
DPL1.4
DPL1.3
DPL1.2
DPL1.1
DL1H.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
7
6
5
4
3
2
1
0
SFR 85h
DPH1.7
DPH1.6
DPH1.5
DPH1.4
DPH1.3
DPH1.2
DPH1.1
DPH1.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Maxim Integrated