Media independent interface (mii) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual

Page 174

High-Speed Microcontroller User’s

Guide: Network Microcontroller

Supplement

174

Table 22-2. MAC Control Register Bit Summary

MEDIA INDEPENDENT INTERFACE (MII)

The DS80C400 fully supports the media-independent interface according to the IEEE 802.3 standard. The MII interface provides inde-

pendent transmit and receive datapaths, as well as input signals for monitoring network status. All standard PHY controller chips can

use this default 4-bit parallel interface for connection to the Ethernet cable.

The transmit interface is composed of TXCLK, TX_EN, and TXD[3:0]. The TXCLK input is the transmit clock provided by the PHY. For

10Mbps operation, the transmit clock (TXCLK) should be run at 2.5MHz. For 100Mbps, TXCLK should be run at 25MHz. The TXD[3:0]

outputs provide the 4-bit (nibble) data bus for transmitting frame data to the external PHY. Each transmission begins when the TX_EN

output is driven active-high, indicating to the PHY that valid data is present on the TXD[3:0] bus.

The receive interface is comprised of RXCLK, RX_DV, RX_ER, and RXD[3:0]. The RXCLK input is the receive clock provided by the

external PHY. This clock (RXCLK) should be run at 2.5MHz for 10Mbps operation and at 25MHz for 100Mbps operation. The RXD[3:0]

inputs serve as the 4-bit (nibble) data bus for receiving frame data from the external PHY. The reception begins when the external PHY

drives the RX_DV input high, signaling that valid data is present on the RXD[3:0] bus. During reception of a frame (RX_DV = 1), the

RX_ER input indicates whether the external PHY has detected an error in the current frame. The RX_ER input is ignored when not receiv-

ing a frame (RX_DV = 0).

The MII also monitors two network status signals that are provided by the external PHY. The carrier sense (CRS) input is used to assess

when the physical media is idle. The collision detect (COL) input is required for half-duplex operation to signal when a collision has

occurred on the physical media. Figure 22-2 shows a full MII interface. Data transactions between the MAC and the external PHY are

done least significant nibble first as shown in Figure 22-3.

OPERATIONAL MODE ==>

HALF-DUPLEX

FULL-DUPLEX

LOOPBACK

Bit 27: Port select

0 = MII, 1 = ENDEC

Bit 28: Heartbeat disable

User-selectable ENDEC only

Invalid–set to 1

Bit 23: Disable receive own

Bits 22-21: Loopback operating mode

01 or 10

Bit 20: Full-duplex mode

Bit 3: Transmitter enable

MAC transmitter enable

Bit 2: Receiver enable

MAC receiver enable

Bit 31: Receive all

Address-filtering control

Bit 19: Pass all multicast

Address-filtering control

Bit 18: Promiscuous

Address-filtering control

Bit 17: Inverse filtering

Address-filtering control

Bit 15: Hash only

Address-filtering control

Bit 13: Hash/perfect filtering

Address-filtering control

Bit 16: Pass bad frames

Packet-filtering control

Bit 11: Disable broadcast frames

Packet-filtering control

Bit 12: Late collision control

CSMA/CD

Invalid–set to 0

Bit 10: Disable retry

CSMA/CD

Invalid–set to 0

Bits 7-6: Back-off limit

CSMA/CD

Invalid–set to 00

Bit 5: Deferral check

CSMA/CD

Invalid–set to 0

Bit 30: Endian mode

User-selectable

Bit 8: Automatic pad stripping

User-selectable

Maxim Integrated