Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual

Page 49

High-Speed Microcontroller User’s

Guide: Network Microcontroller

Supplement

WKS
Bit 5

RXS
Bit 4

TXS
Bit 3

CAN 0 wake-up status. (Read only.) WKS = 0 indicates that the CAN 0 is not in a low-power mode. WKS
= 1 indicates that CAN 0 is in a low-power mode, based on the setting of either the SIESTA bit or the

power-down mode bit to a 1. Clearing both the SIESTA bit and power-down enable (PDE) bit forces the

WKS bit to a 0. A change in the state of WKS from a previous 1 to a 0 generates an interrupt if the STIE,

C0IE, and IE SFR register bits are set.

Receive status. The RXS bit functions in two modes. When the AUTOB bit is set to a 1, RXS = 1 indi-
cates that a message has been successfully received by CAN 0 since the last read of the CAN 0 status

center, but means that the message did not have any errors associated with it during the reception.

Messages that are successfully received but are not stored do not pass the arbitration filtering tests

required by the internal message centers. When the AUTOB bit is cleared to a 0, RXS = 1 indicates that

a message has been both successfully received and stored in one of the message centers by CAN 0

since the last read of the CAN 0 status register.

RXS = 0 indicates that no message has been successfully received since the last read of the CAN 0 sta-

tus register. RXS is set only by the CAN 0 logic and is not cleared by the CAN controller. It is cleared

only by the microcontroller software, the CRST bit, or a system reset.

When the RXS bit (0 > 1) provides the interrupt source for an interrupt, the microcontroller is required to

read the CAN status register to clear the internal status-change interrupt flag. This flag is seen externally

by the presence of the 01 state in the CAN interrupt register. Once this flag is cleared, the 01 state in

the CAN interrupt register is replaced with either the 00 state for no interrupts pending or a lower-prior-

ity interrupt code related to one of the message centers. If a second successful reception is detected

prior to or after the clearing of the RXS bit in the status register, a second status-change interrupt flag is

set to allow a second interrupt to be issued. Each new successful reception generates an interrupt

request independent of the previous state of the RXS bit, as long as the CAN status register has been

read to clear the previous status-change interrupt flag. Note that if the microcontroller sets the RXS bit

from a previous low, it generates an artificial status-change interrupt (STIE = 1).

Thus, if RXS is previously set to 0 and a reception was successful, RXS is set to 1 and an interrupt can

be asserted if enabled. If the microcontroller writes a 1 to RXS when RXS was previously a 0, RXS is set

to a 1 and an interrupt can be asserted if enabled. If RXS is previously set to 1 and a reception was suc-

cessful, RXS stays set to a 1 and an interrupt can be asserted if enabled. If the microcontroller writes a

1 to RXS when RXS was previously a 1, RXS remains 1 and no interrupt is asserted.

Transmit status. TXS = 1 indicates that a message has been successfully transmitted by CAN 0 (error
free and acknowledged) since the last read of the CAN 0 status register. TXS = 0 indicates that no mes-

sage has been successfully transmitted since the last read of the CAN 0 status register. TXS is set only

by the CAN 0 logic and is not cleared by the CAN controller but is cleared only by the microcontroller

software, the CRST bit, or a system reset.

When the TXS bit (0 > 1) provides the interrupt source for an interrupt, the microcontroller is required to

read the CAN status register to clear the internal status-change interrupt flag (this flag is seen external-

ly by the presence of the 01 state in the CAN interrupt register). Once this flag is cleared, the 01 state

in the CAN interrupt register is replaced with either the 00 state for no interrupts pending or a lower-pri-

ority interrupt code related to one of the message centers. If a second successful transmission is detect-

ed prior to or after the clearing of the TXS bit in the status register, a second status-change interrupt flag

is set to allow a second interrupt to be issued. Each new successful transmission generates an interrupt

request independent of the previous state of the TXS bit, as long as the CAN status register has been

read to clear the previous status-change interrupt flag. Note that, if the microcontroller sets the TXS bit

from a previous low, it generates an artificial status-change interrupt (STIE = 1).

Thus, if TXS is previously set to 0 and a transmission was successful, TXS is set to 1 and an interrupt

can be asserted if enabled. If the microcontroller writes a 1 to TXS when TXS was previously a 0, TXS is

set to a 1 and an interrupt can be asserted if enabled. If TXS is previously set to 1 and a transmission

was successful, TXS stays set to a 1 and an interrupt can be asserted if enabled. If the microcontroller

writes a 1 to TXS when TXS was previously a 1, TXS remains 1 and no interrupt is asserted.

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