Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 108)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
108
Write-Protection Feature (DS80C400 Only)
When combined program/data memory access is enabled, there is the potential to inadvertently modify code that one meant to leave
fixed. For this reason, the DS80C400 provides the ability to write protect the first 0–16kB of memory accessible through each of the chip
enables CE3, CE2, CE1, and CE0. The write-protection feature for each chip enable is invoked by setting the appropriate WPE3–0
(MCON2.3–0) bit. The protected range is defined by the WPR2-0 (MCON2.6-4) bit settings as shown in Table 6-7. Any MOVX instruc-
tions attempting to write to a protected area is disallowed and the write-protected interrupt flag (WPIF–MCON2.7) is set by hardware.
Table 6-7. Write-Protection Range
Enhanced Quad Data Pointers
The DS80C400 offers enhanced features for accelerating the access and movement of data. The DS80C400 contains four data point-
ers (DPTR0, DPTR1, DPTR2, and DPTR3) instead of the single data pointer offered on the original 8051. DPTR0 is located at the same
address as the original 8051 data pointer, allowing the DS80C400 to execute standard 8051 code with no modifications. The registers
making up the second, third, and fourth data pointers are located at SFR address locations not used in the original 8051. To access
the extended 24-bit address range supported by the DS80C400, a third, high-order byte (DPXn) has been added to each pointer, so
that each data pointer is now comprised of the SFR combination DPXn + DPHn + DPLn. Table 6-8 summarizes the SFRs that make up
each data pointer.
Table 6-8. Data Pointer SFR Locations
Two bits, SEL1 and SEL located in the data pointer select (DPS: 86h) register, select which one of the four pointers is active. For the
SEL1, SEL bits, the 00b state selects DPTR0, 01b selects DPTR1, 10b selects DPTR2, and 11b selects DPTR3. To allow for code com-
patibility with previous dual data pointer microcontrollers, the bits adjacent to SEL are not implemented so that the INC DPS instruction
can still be used to quickly toggle between DPTR0 and DPTR1 or between DPTR2 and DPTR3. Each data pointer also has an associ-
ated increment/decrement control bit. This bit defines, for each data pointer, whether the INC DPTR instruction increments or decre-
ments the pointer when it is selected. When the active data pointer ID (increment/decrement) control bit is clear (= 0), the INC DPTR
instruction increments the pointer, whereas a decrement occurs if the active pointer’s ID bit is set (= 1) when the INC DPTR instruction
is performed. The increment/decrement control bits for DPTR0, DPTR1 and ID0, ID1 respectively, can be found in the DPS (86h) reg-
ister, while controls for DPTR2, DPTR3 and ID2, ID3 are found in the DPS1 (F6h) register.
ID0 = DPS.6
ID1 = DPS.7
ID2 = DPS1.6
ID3 = DPS1.7
To expedite data transfer and copy routines, the DS80C400 features the ability to automatically advance the data pointer and/or auto-
matically toggle to a different data pointer in response to execution of certain instructions. The autotoggle feature does not toggle
between all four data pointers, nor does it allow the user to select which data pointers to toggle between. When the toggle select bit
DATA POINTER DPX + DPH + DPL COMBINATION
DPTR0 DPX (93h) + DPH (83h) + DPL (82h)
DPTR1 DPX1 (95h) + DPH1 (85h) + DPL1 (84h)
DPTR2 DPX2 (EBh) + DPH2 (F3h) + DPL2 (F2h)
DPTR3 DPX3 (EDh) + DPH3 (F5h) + DPL3 (F4h)
MCON2.6-4 RANGE PROTECTED
000 0–2kB
001 0–4kB
010 0–6kB
011 0–8kB
100 0–10kB
101 0–12kB
110 0–14kB
111 0–16kB
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