Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 176)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
176
ENDEC MODE—HEARTBEAT SIGNAL QUALITY GENERATOR
When operating in ENDEC mode, the heartbeat signal quality generator (SQE) heartbeat function can optionally be enabled by clear-
ing (= 0) the heartbeat disable bit (bit 28) of the MAC control CSR register. When the SQE function has been enabled, after each trans-
mission, the MAC expects to receive a pulse on the COL pin after the TX_EN signal goes inactive. Failure to receive this SQE pulse
from the PHY results in the heartbeat fail bit of the transmit status word being set for the packet. In order to use the SQE function, the
PHY must support the SQE function and the function must be enabled.
MAC PRIMARY FUNCTIONS—PACKET FILTERING
The DS80C400 media access controller (MAC) provides programmable features designed to minimize host supervision and interac-
tion. The MAC independently handles all necessary Ethernet framing and error checking requirements.
For transmission, the MAC automatically generates preamble and start-of-frame delimiter bytes. If the minimum frame length is not met,
the MAC can automatically append zero-padding to the data field such that the frame length exceeds the required minimum length
(46 bytes). The CPU can optionally request, when submitting to the BCU, that the automatic zero-padding not be added to the trans-
mit packet. The MAC dynamically generates and appends the FCS to each transmit packet. Again, the CPU has the option of request-
ing that the FCS not be appended by the MAC. The MAC monitors the CRS and COL network status signals and, according to pro-
grammable MAC control register bit settings, can defer transmission temporarily or indefinitely, can automatically abort or retry collid-
ed frames, and can attempt retransmission according to a variable 1-bit to 10-bit back-off counter.
RXD[3:1]
RXD[0]
RXCLK
NC
MDC
MII
MANAGEMENT
BLOCK
(Serial interface bus
to PHY)
MDIO
MII I/O BLOCK
(Transmit, receive,
and flow control)
EXTERNAL
PHY
DEVICE
TX_EN
TXD[3:1]
RX_DV
RX_ER
CRS
COL
TXCLK
DS80C400
TXD[0]
NC
7 0 7 0
1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0
Bytes transmitted by the MAC
A1h E6h
TXD[0]
(to PHY)
0 1 0 0
TXCLK
(from PHY)
1 0 0 1 0 0 1 1 1 0 1 1
0 (lsb) 1 2 3 4 5 6 7(msb) 0(lsb) 1 2 3 4 5 6 7(msb) ==> bit order (lsb first)
increasing time
Figure 22-5. Serial ENDEC Mode–Byte/Bit Transmit and Receive Order
Figure 22-4. ENDEC Signal Diagram
Maxim Integrated