Can 0 control register (c0c) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual

Page 45

High-Speed Microcontroller User’s

Guide: Network Microcontroller

Supplement

CAN 0 Control Register (C0C)

SFR A3h

ERIE

STIE

PDE

SIESTA

CRST

AUTOB

ERCS

SWINT

RW-0

RT-1

RW-0

RT-1

R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset

This SFR is not present on the DS80C411.

ERIE
Bit 7

STIE
Bit 6

PDE
Bit 5

SIESTA
Bit 4

CAN 0 error interrupt enable. Programming the ERIE bit to a 1 enables the CAN 0 status bus status
(BSS) or error count greater than 96 bit (EC96) to issue an interrupt to the microcontroller, if the C0IE bit

in the EIE SFR is also set. When ERIE is cleared to a 0, the error interrupt is disabled.

CAN 0 status interrupt enable. Programming the STIE bit to a 1 allows the CAN 0 status error bits (ER0-
ER2), the transmit status bit (TXS), the receive status bit (RXS), or the wake-up status bit (WKS) to issue

an interrupt to the microcontroller, if the C0IE bit in the EIE SFR is also set. When STIE is cleared to a 0,

the status interrupt is disabled.

CAN 0 power-down enable. Programming the PDE bit to a 1 places the CAN 0 controller into a fully sta-
tic power-down mode after completion of the last reception, transmission, or after the arbitration was lost

or an error condition occurred. Note that the term ‘after arbitration lost’ denotes the fact the arbitration was

lost and the reception following this lost arbitration is completed. Recall that the CAN processor immedi-

ately becomes a receiver after it has lost its arbitration on the CAN bus. Programming PDE = 0 disables

the power-down mode. The PDE mode forces all of the CAN 0 logic to a static state. The PDE mode can

only be removed by either software reprogramming the PDE bit or through a system reset. A read of PDE

establishes when the power-down mode has been enabled or removed as per the PDE bit. In all cases,

the CAN controller begins operation after 11 recessive bits (a power-up sequence) on the CAN bus per

the configuration settings for bit timing, which were programmed prior to entering the power-down mode.

Since WKS reflects when the CAN has entered the low-power state, as per the SIESTA and/or PDE bit

states, a read of the PDE bit establishes when the PDE bit is actually allowed to enable the low-power

state. If the low-power state was previously enabled by setting the SIESTA bit, a read of PDE reflects the

actual PDE bit value and not the low-power mode. If the low-power mode has not been previously

enabled and the PDE bit is set to a 1 by software, a read of PDE returns a 0, until such time the PDE bit

actually enables the low-power mode following an active transmit or receive operation. When the PDE and

SIESTA bit are not used together, a read of the PDE bit, by default, also reflects the actual state of the low-

power mode. Setting PDE does not alter any CAN block controls or error status relationships.

Low-power mode. Setting the SIESTA bit to a 1 places the CAN 0 controller into a low-power static state
after completion of the last reception, transmission, or after the arbitration was lost or an error condition

occurred. Note that the term ‘after arbitration lost’ denotes the fact the arbitration was lost and the recep-

tion following this lost arbitration is completed. Recall that the CAN processor immediately becomes a

receiver after it has lost its arbitration on the CAN bus. Programming SIESTA = 0 disables the low-power

mode. The state of when the SIESTA mode is actually enabled or removed, as per the SIESTA bit pro-

grammed value, is reflected in the read of the SIESTA bit. The SIESTA mode is removed when the CAN

0 controller detects CAN 0 bus activity, by reprogramming the SIESTA bit to a 0, or by setting either

CRST or SWINT to a 1. When the SIESTA bit is cleared by either a microcontroller write or activity on the

CAN 0 bus, the CAN controller begins operation after 11 recessive bits on the CAN bus (after a power-

up sequence) using the configuration settings that were programmed prior to entering the power-down

mode. Changing the SIESTA bit from a 0 to a 1 does not disrupt a currently active receive or transmit,

but allows the completion of CAN 0 bus activity prior to entering into the static state. If the CAN 0 logic

issues an interrupt as a result of an active CAN 0 receive or transmit while SIESTA is being set, the SIES-

TA bit is cleared, and the CAN 0 logic does not enter the low-power mode. Since WKS reflects when the

CAN has entered the low-power state, as per the SIESTA and/or PDM bit states, a read of the SIESTA

bit establishes when the SIESTA bit is actually allowed to enable the low-power state. If the low-power

state was previously enabled by setting the PDM bit, a read of SIESTA reflects the actual SIESTA bit

value, and not the low-power mode. If the low-power mode has not been previously enabled and the

SIESTA bit is set to a 1 by software, a read of SIESTA returns a 0 until such time that the SIESTA bit actu-

ally enables the low-power mode, following an active transmit or receive operation. When the PDE and

SIESTA bit are not used together, a read of the SIESTA bit, by default, also reflects the actual state of the

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