Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 52)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
52
Description:
1A. STIE = 1 only (polling method: ETI = ERI 0) with no prior interrupt active:
It is important to note that additional changes in bits 4–0 (RXS, TXS) of the CAN 0 status register can be
detected even if these bits have not been cleared by the microcontroller. The only requirement for the
second status-change interrupt is for the microcontroller to read the CAN 0 status register in order to
clear the previous interrupt. Multiple changes in the CAN 0 status register, which are read from the CAN
0 status register and occur without the microcontroller clearing the status-change interrupt, appear as
one interrupt. The WKS bit is a read-only bit and is not altered by a write from the microcontroller, and
the ER2-ER0 bits are automatically set to 111 following a read of the CAN status register.
Although not related to a successful transmission or reception, ERIE = 1 also enables a similar interrupt
relationship when bits 6 or 7 are changed in the CAN status register, with ERIE = 1.
1B. ERIE = 1 with no prior interrupt active:
2. ERI = 1 and/or ETI = 1 only (hardwired method: STIE = 0) with no prior interrupt active:
CASE ERI
RECEPTION
SUCCESSFUL?
INTIN
VECTOR
INTRQ
CAN 0
INT
A 0 No
Value A
or 0
0 Inactive
B 0 Yes
Value A
or 0
0 Inactive
C 1 No
Value A
or 0
0 Inactive
D 1 Yes
Value A
or (MCV
> INTIN)
1 Active
CASE ERIE
CHANGE
DETECTED IN
BIT 7 OR 6 OF
C0S SFR?
INTIN
VECTOR
INTRQ CAN 0 INT
A 0 No
Value A
or 0
Not
affected
Inactive
B 0 Yes
Value A
or 0
Not
affected
Inactive
C 1 No
Value A
or 0
Not
affected
Inactive
D 1 Yes
Value A
or 0 > 1
Not
affected
Active
CASE STIE
CHANGE
DETECTED IN
BIT 5-0 OF C0S
SFR?
INTIN
VECTOR
INTRQ CAN 0 INT
A 0 No
Value A
or 0
Not
affected
Inactive
B 0 Yes
Value A
or 0
Not
affected
Inactive
C 1 No
Value A
or 0
Not
affected
Inactive
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