Serial data buffer 1 (sbuf1), Power-management register (pmr) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 68
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
68
Serial Data Buffer 1 (SBUF1)
Power-Management Register (PMR)
TB8_1
Bit 3
RB8_1
Bit 2
TI_1
Bit 1
RI_1
Bit 0
9th transmission bit state. This bit defines the state of the 9th transmission bit in serial port 1, modes
2 and 3.
9th received bit state. This bit identifies the state of the 9th bit of received data in serial port 1, modes
2 and 3. When SM2_1 is 0, it is the state of the stop bit in mode 1. This bit has no meaning in mode 0.
Transmitter interrupt flag. This bit indicates that the data in the serial port 1 buffer has been completely
shifted out. It is set at the end of the last data bit for all modes of operation and must be cleared by software.
9th received bit state. This bit identifies the state of the 9th bit of received data in serial port 1, modes
2 and 3. When SM2_1 is 0, it is the state of the stop bit in mode 1. This bit has no meaning in mode 0.
Receive interrupt flag. This bit indicates that a data byte has been received in the serial port 1 buffer.
It is set at the end of the 8th bit for mode 0, after the last sample of the incoming stop bit for mode 1
subject to the value of the SM2_1 bit, or after the last sample of RB8_1 for modes 2 and 3. This bit must
be cleared by software.
7
6
5
4
3
2
1
0
SFR C1h
SBUF1.7
SBUF1.6
SBUF1.5
SBUF1.4
SBUF1.3
SBUF1.2
SBUF1.1
SBUF1.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
7
6
5
4
3
2
1
0
SFR C4h
CD1
CD0
SWB
CTM
4X/2X
ALEOFF
—
—
R*-1
R*-0
RW-0
R*-0
R*-0
RW-0
R-1
R-0
R = Unrestricted read, W = Unrestricted write, * = See description, -n = Value after reset
SBUF1.7–0
Bits 7–0
Serial data buffer 1. Data for serial port 1 is read from or written to this location. The serial transmit and
receive buffers are separate registers, but both are addressed at this location.
CD1, CD0
Bits 7–6
Clock divide control bits 1 and 0. These bits select the number of crystal oscillator clocks required to
generate one machine cycle. Switching between modes requires a transition through the divide-by-4
mode (CD1, CD0 = 01). For example, to go from 1 to 1024 clocks-per-machine cycle, the device must
first go from 1 to 4 clocks per cycle and then from 4 to 1024 clocks per cycle. Attempts to perform an
invalid transition are ignored. The setting of these bits affects the timers and serial ports, as shown in
the following table:
Attempts to change these bits to the frequency multiplier setting (one or two clocks per cycle) fail when
running from the internal ring oscillator. In addition, it is not possible to change these bits to the 1024
clocks-per-machine cycle setting while the switchback enable bit (SWB) is set and any of the switch-
back sources (external interrupts or serial port transmit or receive activity) are active.
OSC CYCLES PER
TIMER 0/1/2 CLOCK
OSC CYCLES PER
SERIAL PORT CLK,
MODE 0
OSC CYCLES PER
SERIAL PORT CLK,
MODE 2
CD1:0
4X/2X
OSCILLATOR
CYCLES PER
MACHINE
CYCLE
TXM = 0
TXM = 1
OSC CYCLES
PER TIMER 2
CLK, BAUD
RATE GEN
SM2 = 0
SM2 = 1
SMOD = 0
SMOD = 1
00
1
1
12
1
2
3
1
64
32
00
0
2
12
2
2
6
2
64
32
01
x
Reserved
10
x
4
12
4
2
12
4
64
32
11
x
1024
3072
1024
512
3072
1024
64
32
Maxim Integrated