Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 65)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
65
Interrupt Priority (IP)
7 6 5 4 3 2 1 0
SFR B8h — PS1 PT2 PS0 PT1 PX1 PT0 PX0
— RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset, IP is set to 80h on all forms of reset.
Slave Address Mask Enable Register 0 (SADEN0)
Bit 7
PS1
Bit 6
PT2
Bit 5
PS0
Bit 4
PT1
Bit 3
PX1
Bit 2
PT0
Bit 1
PX0
Bit 0
Reserved. Read data is indeterminate.
Serial port 1 interrupt. This bit controls the priority of the serial port 1 interrupt.
0 = Serial port 1 is a low priority.
1 = Serial port 1 is a high-priority interrupt.
Timer 2 interrupt. This bit controls the priority of timer 2 interrupt.
0 = Timer 2 is a low priority.
1 = Timer 2 is a high-priority interrupt.
Serial port 0 interrupt. This bit controls the priority of the serial port 0 interrupt.
0 = Serial port 0 is a low priority.
1 = Serial port 0 is a high-priority interrupt.
Timer 1 interrupt. This bit controls the priority of timer 1 interrupt.
0 = Timer 1 is a low priority.
1 = Timer 1 is a high-priority interrupt.
External interrupt 1. This bit controls the priority of external interrupt 1.
0 = External interrupt 1 is a low priority.
1 = External interrupt 1 is a high-priority interrupt.
Timer 0 interrupt. This bit controls the priority of timer 0 interrupt.
0 = Timer 0 is a low priority.
1 = Timer 0 is a high-priority interrupt.
External interrupt 0. This bit controls the priority of external interrupt 0.
0 = External interrupt 0 is a low priority.
1 = External interrupt 0 is a high-priority interrupt.
7 6 5 4 3 2 1 0
SFR B9h SADEN0.7 SADEN0.6 SADEN0.5 SADEN0.4 SADEN0.3 SADEN0.2 SADEN0.1 SADEN0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
SADEN0.7–0
Bits 7–0 Slave address mask enable register 0. This register is a mask enable when comparing serial port 0
addresses for automatic address recognition. When a bit is set in this register, the corresponding bit
location in the SADDR0 register is exactly compared with the incoming serial port 0 data to determine
if a receive interrupt should be generated. When a bit in this register is cleared, the corresponding bit
in the SADDR0 register becomes a “don’t care” and is not compared against the incoming data. All
incoming data generates a receive interrupt when this register is cleared.
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