Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 186)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
186
RECEIVING DATA
After configuring the Ethernet MAC and the defining the receive buffer size, reception, and storage of data from the MII or ENDEC, the
interface does not require CPU intervention. The MAC operates per the settings specified in the CSR registers. The BCU automatical-
ly stores received data and receive status words to the receive data buffer when open pages are available and updates the receive
FIFO. The CPU needs only to process receive data buffer entries and maintain sufficient open pages in the receive data buffer for addi-
tional packet storage by the BCU. From the CPU’s perspective, the receive operation begins when the receive interrupt flag (RIF) is
set by the BCU. If the Ethernet activity interrupt source is enabled, this event generates an interrupt request to the CPU. If the Ethernet
activity interrupt source is not enabled, some polling scheme must be used to determine when an Ethernet packet has been received.
The CPU then reads the BCUD SFR to acquire packet size/location information from the receive FIFO. Using this information, the CPU
can locate the receive status word for the packet and process the packet accordingly. Once the CPU finishes processing the receive
data buffer, it must invalidate the current receive packet in order to release the associated receive buffer pages for future use. Once
the current receive packet has been invalidated, the next entry in the receive FIFO (if not empty) can then be accessed through the
BCUD SFR. Note that the RIF flag serves as an indicator as to whether the receive FIFO is empty and therefore should always be
cleared before invalidating the current receive packet to prevent missing an RIF = 1 condition. As an alternate means to free receive
data memory, the receive FIFO and all receive buffer pages can be flushed by issuing the flush receive buffer command. A simple flow
diagram for the receive process is provided in the following figure.
Figure 22-13. Receive Flow Diagram
Process receive data buffer memory (MOVXs)
Write BCUC SFR to free receive buffer memory
BCUC.3-0 Command
0010 Invalidate current receive packet
0011 Flush receive buffer
CPU
ETHERNET CONTROLLER
BCU
CPU RUNS OTHER
APPLICATION CODE
BCU receives data from MAC*
1) Confirms open page in receive data buffer
2) Store receive data in receive buffer memory
3) Write receive status word
4) Update receive FIFO with start page, number of page
5) Receive interrupt flag (RIF) set to 1
Ethernet activity interrupt request (if enabled)
1) Read BCUC to find RIF = 1
2) Read receive FIFO (BCUD)
BCUD.7-5 = #pages [001–110b]
BCUD.4-0 = start page [00000–11111b]
3) Read receive status word for packet handling
* Notes for the above steps:
1) If the BCU determines that no open pages are
available in the receive data buffer (RBF = 1)
the receive operation cannot occur. Steps 2–5
are not executed. Enabling flow control
would require that at least five pages be
available to avoid assertion of back pressure.
Setting the FPE bit would mandate that the
destination address filter criteria be met
before storing to the receive data buffer.
2) If the receive data buffer becomes full during
a receive operation, RBF is set to 1 and the
current reception is aborted. Steps 2–5 are
executed for the aborted operation.
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