Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 72)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
72
Timer 2 Control (T2CON)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
7 6 5 4 3 2 1 0
SFR C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
TF2
Bit 7
EXF2
Bit 6
RCLK
Bit 5
TCLK
Bit 4
EXEN2
Bit 3
TR2
Bit 2
C/ T2
Bit 1
CP/ RL2
Bit 0
Timer 2 overflow flag. This bit is set when timer 2 overflows from FFFFh or the count is equal to the cap-
ture register in down-count mode. It must be cleared by software. This bit can only be set if RCLK and
TCLK are both cleared to 0.
Timer 2 external flag. A negative transition on the T2EX (P1.1) causes this flag to be set if (CP/PL2 =
EXEN2 = 1) or (CP/PL2 = DCEN = 0 and EXEN2 = 1). When CP/PL2 = 0 and DCEN = 1, this bit toggles
whenever timer 2 underflows or overflows. In this mode, EXF2 can be used as the 17th timer bit and
does not cause an interrupt. If set by a negative transition, this flag must be cleared by software. Setting
this bit forces a timer interrupt, if enabled.
Receive clock flag. This bit determines the serial port 0 time base when receiving data in serial modes
1 or 3. Setting this bit to 1 causes timer 2 overflow to be used to determine receive baud rate and forces
timer 2 into baud-rate generation mode, which operates from divide-by-2 of the external clock. Clearing
this bit to 0 causes timer 1 overflow to be used.
Transmit clock flag. This bit determines the serial port 0 time base when transmitting data in serial
modes 1 or 3. Setting this bit to 1 causes timer 2 overflow to be used to determine transmit baud rate
and forces timer 2 into baud-rate generation mode, which operates from divide-by-2 of the external
clock. Clearing this bit to 0 causes timer 1 overflow to be used.
Timer 2 external enable. Setting this bit to 1 enables the capture/reload function on the T2EX (P1.1) pin
for a negative transition, if timer 2 is not generating baud rates for the serial port. Clearing this bit to 0
causes timer 2 to ignore all external events on T2EX pin.
Timer 2 run control. This bit enables timer 2 operation when set to 1. Clearing this bit to 0 halts timer
2 operation and preserves the current count in TH2 and TL2.
Counter/timer select. This bit determines whether timer 2 functions as a timer or counter. Setting this
bit to 1 causes timer 2 to count negative transitions on the T2 (P1.0) pin. Clearing this bit to 0 causes
timer 2 to function as a timer. The speed of timer 2 is determined by the T2M (CKCON.5) bit. Timer 2
operates from divide-by-2 external clock when used in either baud-rate generator or clock output mode.
Capture/reload select. This bit determines whether the capture or reload function is used for timer 2. If
either RCLK or TCLK is set, timer 2 functions in an autoreload mode following each overflow. Setting this
bit to 1 causes a timer 2 capture to occur when a falling edge is detected on T2EX if EXEN2 is 1.
Clearing this bit to 0 causes an autoreload to occur when timer 2 overflow, or a falling edge, is detect-
ed on T2EX if EXEN2 is 1.
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