Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 56)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
56
CAN 0 Message Center 1 Control Register (C0M1C)
Slave Address Register 1 (SADDR1)
7 6 5 4 3 2 1 0
SFR ABh MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP
RW-0 RW-0 RW-0 RW-0 RC-0 R*-0 R*-0 R*-0
R = Unrestricted read, C = Clear only, * = See description, -n = Value after reset
This SFR is not present on the DS80C411.
7 6 5 4 3 2 1 0
SFR A9h SADDR0.7 SADDR0.6 SADDR0.5 SADDR0.4 SADDR0.3 SADDR0.2 SADDR0.1 SADDR0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
SADDR1.7–0
Bits 7–0 Slave address register 1. This register is programmed with the given or broadcast address assigned
to serial port 1.
COM1C
Bits 7–0
MSRDY
Bit 7
ETI
Bit 6
ERI
Bit 5
INTRQ
Bit 4
Read/write access. MSRDY, ETI, ERI, and INTRQ are unrestricted read/write bits. EXTRQ is read/clear
only. When T/R = 0, ROW is read only. When T/R = 1, TIH is unrestricted read/write. MTRQ is unrestrict-
ed read and can only be set to a 1 when written to by the microcontroller or by the CAN controller, in
case of a remote frame reception in a transmit message center. A write of a 0 to MTRQ leaves the MTRQ
bit unchanged. DTUP is unrestricted read. When T/R = 0, DTUP can only be cleared to a 0 when writ-
ten to by the microcontroller. A write of a 1 to DTUP with T/R = 0 leaves the DTUP bit unchanged. DTUP
is unrestricted read/write when T/R = 1.
CAN 0 message center 1 ready. (MSRDY is unrestricted read/write.) MSRDY is programmed
by the microcontroller to notify the CAN 0 logic when the associated message is ready for communica-
tion on the CAN 0 bus. When MSRDY = 0, the CAN 0 processor does not access this message center
for transmissions or to receive data or remote frame requests. MSRDY = 1 indicates the message is
ready for communication, and MSDRY = 0 indicates either that the associated message is not config-
ured for use or that it is not required at the present time. This bit is used by the microcontroller to pre-
vent the CAN 0 logic from accessing a message while the microcontroller is updating message attrib-
utes. These include as identifiers: arbitration registers 0–3, data byte registers 0–7, data byte count
(DTBYC3, DTBYC0), direction control (T/R), the extended or standard mode bit (EX/ST), and the mask
enables (MEME and MDME) associated with message 1. MSRDY is cleared to a 0 following a micro-
controller hardware reset or a reset generated by the CRST bit in the CAN 0 control register, and must
also remain in a cleared mode until all the CAN 0 initialization has been completed. Individual message
MSRDY controls can be changed after initialization to reconfigure specific messages, without interrupt-
ing the communication of other messages on the CAN 0 bus.
CAN 0 message center 1 enable transmit interrupt. (ETI is unrestricted read/write.) When ETI is
cleared to 0, a successful transmission does not set INTRQ and, as such, does not generate an inter-
rupt. Setting ETI to a 1 enables a successful CAN 0 transmission to set the INTRQ bit, which in turn
issues an interrupt to the microcontroller. Note that the ETI bit located in message center 15 is ignored
by the CAN processor, since the message center 15 is a receive-only message center.
CAN 0 message center 1 enable receive interrupt. (ERI is unrestricted read/write.) When ERI is
cleared to 0, a successful reception does not set the INTRQ and, as such, does not generate an inter-
rupt. When the ERI is set to a 1, the INTRQ bit is only set when the CAN processor successfully receives
and stores the incoming message into one of the message centers. Setting INTRQ, in turn, issues an
interrupt request to the microcontroller.
Interrupt request. (INTRQ is unrestricted read/write.) INTRQ is automatically set to a 1 by the CAN 0
logic when the ERI is set and the CAN 0 logic completes a successful reception and store. The INTRQ
bit is also set to a 1 when the ETI is set and the CAN 0 logic completes a successful transmission. The
INTRQ interrupt request must also be enabled by the EA global mask in the IE SFR register if the inter-
rupt is to be acknowledged by the microcontroller interrupt logic.
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