Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 180)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
180
The MAC also can transmit a pause control frame on the request from the application. To initiate a pause control frame, the desired
pause time [15:0] interval should first be written to the flow control register. The application must then write a 1 to the BUSY bit of the
flow control register to trigger the transmission. The MAC constructs a pause control frame using these values and transmits the frame
to the MII interface. The transmission of the pause control frame does not affect, and is not affected by, the state of the pause timer,
which could be running because a previously received pause control frame. Upon the completion of the pause control frame trans-
mission, the FCB bit is cleared. Note that the user should check the state of the FCB bit before writing to the flow control register when
initiating a pause control frame. When the FCB is set to a 1, it signifies a pause control frame transmission is still in progress.
LOOPBACK MODES
The DS80C400 implements two diagnostic loopback modes: internal loopback through the MII and external loopback through the PHY.
To support either of the loopback modes, the MAC must be configured identically to the normal full-duplex operating mode, except for
the bits used to select the loopback mode. The loopback mode is controlled by the loopback operating mode bits (OM[1:0]) of the
MAC control (00h) CSR register. The OM[1:0] bits default to the 00b state for normal operation with no loopback. Internal loopback
through the MII is selected by configuring the OM[1:0] bits to the 01b state. In the internal loopback mode, TXD[3:0] is looped back
internally to RXD[3:0], TX_EN is looped back internally to RX_DV and CRS, and TXCLK (sourced from the PHY) is looped back inter-
nally to RXCLK. RX_ER is internally sampled low by the MAC, and COL is ignored due to full-duplex operation. The internal loopback
mode maps the MII interface pins as diagrammed in Figure 22-8.
Figure 22-8. Internal Loopback Mode (MAC Control OM1:0 = 01b)
The external loopback mode is selected by configuring the OM[1:0] bits to the 10b state. The external loopback mode first requires
that the serial MII management bus (MDC, MDIO) be used to configure the external PHY for local loopback operation. Once the PHY
is placed into the loopback mode, it disregards activity on the physical layer but forces transmissions made by the DS80C400 trans-
mit interface to be looped back to the receive interface. In external loopback mode, the DS80C400 MAC behaves exactly as if it were
in the normal full duplex mode, requiring that the external PHY perform the signal loopback function. The external loopback mode is
diagrammed in the following figure.
MDC
MII MANAGEMENT
BLOCK
(Serial interface bus to
PHY) MDIO
MII I/O BLOCK
(Transmit, receive,
and flow control)
EXTERNAL
PHY
DEVICE
TX_EN
TXD[3:0]
RXCLK
RX_DV
RX_ER
RXD[3:0]
CRS
COL
TXCLK
DS80C400
Maxim Integrated