Address control register (acon) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual

Page 40

High-Speed Microcontroller User’s

Guide: Network Microcontroller

Supplement

Address Control Register (ACON)

SFR 9Dh

—

MROM

BPME

BROM

AM1

AM0

RT-1

RT-0

RT-X

RT-0

R = Unrestricted read, T = Timed access write only, -n = Value after reset. The address control register is cleared to 1100 x 000b on all forms of reset, but bit 3 is reset to

0 on power-on reset.

Bits 7-6

MROM
Bit 5

Reserved.

Merge ROM assignment. The MROM bit provides a software mechanism for mapping the lower 32kB
internal ROM block to one of the two following address locations. The upper 32kB internal ROM block

is always mapped to FF8000h–FFFFFFh of the program memory space.

MROM

LOWER 32kB ROM MEMORY LOCATION (HEX)

000000–007FFF (reset default)

FF0000–FF7FFF

BPME
Bit 4

BROM
Bit 3

SA
Bit 2

AM1, AM0
Bits 1-0

Breakpoint mode enable. Setting this bit to 1 enables the software breakpoint mode. Once enabled,
the processor can enter or exit the breakpoint mode by executing an A5h instruction. Clearing this bit

to 0 disables the A5h instruction to the processor, and no breakpoint mode operation is allowed.

Bypass ROM. This bit determines whether the program flow is to start in the external user program or
the internal ROM after a reset. A 0 forces the processor to start execution at location 000000h of inter-

nal ROM after a reset if the EA pin is connected high. A 1 forces the processor to start user program

execution at location 000000h of the program memory after a reset if the EA pin is connected high.

Connecting the EA pin to ground always forces the processor to start user program execution at loca-

tion 000000h of the program memory after a reset, regardless of the logic state of the BROM bit. This bit

is reset to 0 upon power-on. Changing this bit from a 0 to a 1 when the EA pin is connected high caus-

es a reset immediately. Changing this bit from a 1 to a 0 has no immediate effect on the system function

until a reset occurs.

Extended stack address mode enable. Programming the SA bit to a 0 enables the standard 256
scratchpad SRAM bytes as the default stack. In this mode, the standard 8-bit stack pointer value is sup-

plied by the SP register. ESP is not used in this mode. Programming the SA bit to a 1 enables the alter-

nate use of 1kB of the internal data memory as the stack memory. In this mode, the 2 least significant

bits of the ESP register are used as the two most significant bits of the 10-bit stack pointer.

Address mode control bits.

The AM0 and AM1 bits establish the addressing mode for the microcontroller.

Programming AM1 and AM0 to a 00 leaves the microcontroller in the traditional 8051 16-bit addressing

mode. In this mode, the processor operates with a 16-bit address field with the higher-order program

counter byte (PC23:16) forced to 00h.

Programming AM1 and AM0 to a 01 enables the 24-bit paged addressing mode. In this mode, the

processor operates with a 24-bit address field with the address page register (AP) functioning as the

input source to load the high-order program counter byte (PC23:16) during the execution of specific

instructions.

AM1 AM0

ADDRESSING MODE

16-bit addressing mode

(A23–A16 are locked to 00h)

24-bit paged addressing mode

24-bit contiguous addressing mode

Maxim Integrated