Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 170)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
170
MOV OWMDR, #0AAh ; Load up the byte to be transmit
LCALL Wait4int ; Loop until the byte has been sent
MOV A, OWMDR ; Read the byte received to check against the value sent
As stated before, if performing a READ function, the byte transmitted should be 0FFh, and then the value read from the TX/RX register
would have reflected the value sent by the slave(s).
SEARCH ROM ACCELERATOR
The 1-Wire bus master supports a search ROM-accelerator mode to expedite learning of ROM IDs for those devices connected to the
bus. The bus master must determine the ROM IDs of the slave devices on the 1-Wire bus before it can address each slave device indi-
vidually.
The search ROM command (F0h) is used by the bus master to signal external 1-Wire devices that a ROM ID search will be conduct-
ed. The search ROM command can be issued immediately following a reset sequence initiated by the master. Once the search ROM
command has been issued by the bus master, slave devices simultaneously transmit, bit-by-bit, their unique ROM IDs. Listed below
are the three 1-Wire bus time slots associated with each ROM ID bit acquistion.
Time Slots for Each ROM ID Bit Acquisition:
1) Read time slot—each slave transmits a single bit of its ROM ID (LSB first).
2) Read time slot—each slave transmits a complementary bit to that transmitted in 1.
3) Write time slot—bus master transmits discrepancy decision bit if needed.
The ROM ID acquisition and selection process listed above starts with the least significant bit of each slave device. If the ROM ID bits
match for all currently selected slave devices, the two read time slots reflect complementary data and the bus master does not need
to deselect or remove any slave devices from the selection process. The bus master simply repeats the time slot 1 read data as its write
data for time slot 3 and continues to the next higher ROM ID bit acquistion period. Since it is expected that all 1-Wire devices have
unique ROM IDs, time slots 1 and 2 above inevitably result in conflicting data being driven on the bus for at least one bit position when
multiple slaves are connected. When this occurs, the wired-AND line state yields a 0 for time slots 1 and 2. At this point, the master has
to send a bit value 1 or 0 to select the devices that remain in the search process. All deselected devices are idle until they receive a
reset pulse. The four possible scenarios for slave ROM ID read time slots are shown in Table 21-1.
Table 21-1. ROM ID Read Time Slot Possibilities
The general principle of this search process is to deselect slave devices at every conflicting bit position. At the end of each ROM search
process, the master has learned another ROM ID. A pass of search process takes 64 reading/selection cycles for the master to learn
one device’s ROM ID. Each reading/selection cycle, as noted above, consists of two read time slots and a write time slot. Subsequent
search passes are performed identically to the last up until the point of the last decision. For details about search ROM algorithm in the
1-Wire system, refer to The Book of iButton Standards.
To speed up this ROM ID search process, the 1-Wire bus master incorporates a search ROM accelerator. To enable the search ROM
accelerator, the SRA bit in the command register must be set immediately following the reset sequence and issuance of the search
ROM command. After the bus master is placed in search ROM accelerator mode, each byte loaded into the transmit buffer contains
one nibble (4 bits) worth of discrepancy decision data. The two slave read time slots are automatically generated by the bus master as
a part of the transmit sequence. After four reading/selection cycles, the receive buffer data reflects four newly acquired bits of the ROM
ID and four corresponding bits flagging whether a discrepancy existed in a given bit position. The format for the transmit and receive
data (when in search ROM accelerator mode) is detailed in Table 21-2.
READ TIME SLOT 1
(SLAVE)
READ TIME SLOT 2
(SLAVE)
WRITE TIME
SLOT (MASTER)
FUNCTION
0 1 0
All slave devices remaining in the selection process have a 0
in this ROM ID bit position.
1 0 1
All slave devices remaining in the selection process have a 1
in this ROM ID bit position.
0 0 0 or 1
ID discrepancy—slave devices remaining in the selection
process have both 0 and 1 in this ROM ID bit position. The
bus master write time slot dictates which devices remain in
the selection process.
1 1 1 Error—no slave devices responded during the read time slots.
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