Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 171)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
171
Table 21-2. Transmit/Receive Byte Sequence
r n = decision discrepancy data (write time slot selection data if ID discrepancy)
ID n = selected ROM ID bit (r n if discrepancy occurred, otherwise read time slot 1)
d n = discrepancy detected flag (ID discrepancy or no response)
x = don’t care data
The CPU must send and receive 16 bytes of data to complete a single search ROM pass on the 1-Wire bus. To perform a search ROM
sequence one starts with all decision discrepancy bits (rn) being 0. In case of bus error, all subsequent response bits IDn are 1s until
the search accelerator is deactivated by clearing the SRA bit in the command register. Thus, if ID63 and d63 are both 1, an error has
occurred during the search process and the last sequence has to be repeated. Otherwise, ID63:0 is the ROM code of the device that
has been found and addressed. For the next search ROM sequence one reuses the previous set r n (for n = 0:63), changing to 1 only
that bit position where the highest discrepancy was detected (dn flags). This process is repeated until the highest discrepancy occurs
in the same bit position for two passes, then the next lower discrepancy flag is used for next search. When the search ROM process is
completed, the SRA bit should be cleared in order to release the 1-Wire master from search ROM Accelerator mode.
Accelerated ROM Search Example
The following example should provide a better understanding of how the search ROM Accelerator functionality allows the 1-Wire mas-
ter to identify four different devices on the 1-Wire bus. The ROM contents of the devices is as shown (LSB first):
ROM1 = 00110101....
ROM2 = 10101010....
ROM3 = 11110101....
ROM4 = 00010001....
1. The host issues a reset pulse by writing 01h to the command register. All slave devices respond simultaneously with a presence
detect.
2. The host issues a search ROM command by writing 0Fh to the transmit buffer.
3. The host places the 1-Wire master in search ROM Accelerator mode by writing 02h to the command register.
4. The host writes 00h to transmit buffer and reads the return data from the receive buffer. This process is repeated for total of 16
bytes. The data read contains ROM4 in the ID bit locations and the discrepancy flags d0 and d2 are set. This can easily be seen
by examining the ROM IDs bit by bit. The first discrepancy occurs in bit position 0 (d0). The bus master write time slot contains a
0, thus deselecting ROM2 and ROM3. A discrepancy between ROM1 and ROM4 then occurs in bit position 2 (d2), leaving only
ROM4 in the search. The receive data is as follows: (d0ID0 d1ID1 d2ID2 d3ID3 d4ID4 d5ID5 d6ID6 d7ID7 ….):
5. Receive Data = 10 00 10 01 00 00 00 01....
6. The host then deinterleaves the data to arrive at a ROM ID of 00010001... and discrepancy data (bold) of 10100000…. with the last
discrepancy at location d2.
7. The host writes 0x00h to the command register to exit accelerator mode. The host is now free to send a command or read data
directly from this device.
8. Steps 1 to 6 are now repeated to find the next device on the bus. The 16 bytes of data transmitted this time are identical to ROM4
up until the last discrepancy flag (d2 in this case), which is inverted and all higher order decision discrepancy data bits are set to
0 as shown: r0r1r2r3r4r5…. = 001000….. . For this search iteration, the receive data contains ROM1 in the ID bit locations, again
with discrepancy flags d0 and d2 set. Receive Data = 10 00 11 01 00 01 00 01….
BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Byte 1
Transmit Buffer r 3 x r 2 x r 1 x r 0 x
Receive Buffer ID 3 d 3 ID 2 d 2 ID 1 d 1 ID 0 d 0
Byte 2
Transmit Buffer r 7 x r 6 x r 5 x r 4 x
Receive Buffer ID 7 d 7 ID 6 d 6 ID 5 d 5 ID 4 d 4
. . . .
Byte 16
Transmit Buffer r 63 x r 62 x r 61 x r 60 x
Receive Buffer ID 63 d 63 ID 62 d 62 ID 61 d 61 ID 60 d 60
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