Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 57)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
57
EXTRQ
Bit 3
MTRQ
Bit 2
ROW/TIH
Bit 1
External transmit request. (Read/clear only.) When EXTRQ is cleared to a 0, there are no pending
requests by external CAN nodes for this message. When EXTRQ is set to a 1, a request has been made
for this message by an external CAN node, but the service request has not been completed by the CAN
0 controller at the time of the read of EXTRQ. Following the completion of a requested transmission by
a message center programmed for transmission (T/R = 1), the EXTRQ bit is cleared by the CAN 0 con-
troller. A remote request is only answered by a message center programmed for transmission (T/R = 1)
when DTUP = 1 and TIH = 0 (i.e., when new data was loaded and is not being currently modified by the
micro). Note that a message center programmed for a receive mode (T/R = 0) also detects a remove
frame request and sets the EXTRQ bit in a similar manner, but it does not automatically transmit a data
frame and, as such, does not automatically clear the EXTRQ bit.
Microcontroller transmit request. MTRQ is unrestricted read and can only be set to a 1 when written
to by the microcontroller. A write of a 0 to MTRQ leaves the MTRQ bit unchanged. MTRQ can only be
cleared as a result of a successful transmission by the respective message center, or when the CRST
bit is set or the CAN processor experiences a system reset from the reset sources outlined in the func-
tional description in the reset option and reset timing section of this user’s guide supplement.
The MTRQ is a read-limited write bit, and is designed to allow the microcontroller to request a message
to be transmitted. MTRQ is programmed to a 1 when the microcontroller is requesting the respective
message to be transmitted. MTRQ remains set until such time that the message transmission is suc-
cessfully completed, at which time the CAN 0 controller clears the MTRQ bit. Setting MTRQ with T/R = 1
(directional = transmit) results in the sending of a data frame for the transmitted message, and setting
MTRQ with T/R = 0 (directional = receive) results in the sending of a remote frame request. When the
associated message is programmed for transmit (T/R = 1), the MTRQ bit is also set by the CAN 0 con-
troller at the same time that the EXTRQ bit is set by a message request from an external node. MTRQ is
cleared by the CAN 0 controller at the same time as the EXTRQ bit, once a successful transmission of
the message is completed. Note that the MTRQ bit located in message center 15 is ignored by the CAN
processor, since the message center 15 is a receive-only message center.
Receive overwrite/transmit inhibit. The receive overwrite (ROW) and transmit inhibit (TIH) bits share
the same bit 1 location in the CAN 0 message control register. The ROW function is only supported when
the associated message is programmed by the T/R = 0 bit in the message format register to function in
the receive mode. Similarly, the TIH function is only supported when the associated message is pro-
grammed by the T/R = 1 bit in the message format register to function in the transmit mode.
Receive overwrite. (T/R = 0, ROW is read only.) The ROW is automatically set to a 1 by the CAN 0 con-
troller if a new message is received and stored while the DTUP bit is still set. When set, ROW indicates
that the previous message was potentially lost and may not have been read, since the microcontroller
had not cleared the DTUP bit prior to the new load. When ROW = 0, no new message has been received
and stored while DTUP was set to 1 since this bit was last cleared. Note that the ROW bit is not set when
the WTOE bit is cleared to a 0, since all overwrites are disabled. Thus, if the incoming message match-
es the respective message center and DTUP = 1 in the respective message center, the combination of
WTOE = 0 and DTUP = 1 forces the CAN processor to ignore the respective message center when the
CAN is processing the incoming data.
ROW is cleared by the CAN processor when the microcontroller clears the DTUP bit associated with the
same message center. It must be pointed out that the ROW bit for message center 15 is related to the
overwrite of the buffer associated with message center 15, as opposed to the actual message center
15. ROW reflects the actual message center relationships for message centers 1–14. The ROW bit for
the message center 15 shadow buffer is cleared, once the shadow buffer is loaded into the message
center 15 and the shadow buffer is cleared to allow a new message to be loaded. The shadow buffer is
automatically loaded into message center 15 when the microcontroller clears the DTUP and EXTRQ bits
in message center 15.
Transmit inhibit. (T/R = 1, TIH is unrestricted read/write.) The TIH allows the microcontroller to disable the
transmission of the message when the data contents of the message are being updated. TIH = 1 directs
the CAN 0 controller not to transmit the associated message. TIH = 0 enables the CAN 0 controller to trans-
mit the message. If TIH = 1, EXTRQ is set to a 1 when a remote frame request is received by the message
center. Following the remote frame request and after the microcontroller has established the proper data
to be sent, the microcontroller clears the TIH bit to a 0, which allows the CAN processor to send the data
requested by the previous remote frame request. Note that the TIH bit located in message center 15 is
ignored by the CAN processor, since message center 15 is receive-only.
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