Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual

Page 102

High-Speed Microcontroller User’s

Guide: Network Microcontroller

Supplement

102

Table 6-6 illustrates how program memory is segmented based on the setting of the port 4 configuration control bits (P4CNT.5-3).

Table 6-6. Program Memory Chip-Enable Boundaries

Following any reset, the device defaults to 16-bit mode addressing (ACON.1-0 = 00b), with P6.5, P6.4, and P4.7–P4.4 serving as

address lines (P4CNT.5-3 = 111b) and P4.3–P4.0 configured as CE3-0 (P4CNT.2-0 = 111b). The first program fetch is performed from

000000h with CE0 active (low).

Figures 6-4 and 6-5 illustrate the multiplexed (MUX = 0) and demultiplexed (MUX = 1) external memory interfaces. Both examples

access 512kB of program memory and 256kB of data memory.

P4CNT.5-3

➞

000h

(32kB/CE)

001h

(128kB/CE)

010h

(256kB/CE)

011h

(512kB/CE)

100h

(1MB/CE)

101h

(2MB/CE)

101h

(4MB/CE)

CE0

0h–

7FFFh

0h–

1FFFFh

0h–

3FFFFh

0h–

7FFFFh

0h–

FFFFFh

0h–

1FFFFFh

0h–

3FFFFFh

CE1

8000h–

FFFFh

20000h–

3FFFFh

40000h–

7FFFFh

80000h–

FFFFFh

100000h–

1FFFFFh

200000h–

3FFFFFh

400000h–

7FFFFFh

CE2

10000h–

17FFFh

40000h–

5FFFFh

80000h–

BFFFFh

100000h–

17FFFFh

200000h–

2FFFFFh

400000h–

5FFFFFh

800000h–

BFFFFFh

CE3

18000h–

FFFFh

60000h–

7FFFFh

C0000h–

FFFFFh

180000h–

1FFFFFh

300000h–

3FFFFFh

600000h–

7FFFFFh

C00000h–

FFFFFFh

CE4

20000h–

27FFFh

80000h–

9FFFFh

100000h–

13FFFFh

200000h–

27FFFFh

400000h–

4FFFFFh

800000h–

9FFFFFh

—

CE5

28000h–

2FFFFh

A0000h–

BFFFFh

140000h–

17FFFFh

280000h–

2FFFFFh

500000h–

5FFFFFh

A00000h–

BFFFFFh

—

CE6

30000h–

37FFFh

C0000h–

DFFFFh

180000h–

1BFFFFh

300000h–

37FFFFh

600000h–

6FFFFFh

C00000h–

DFFFFFh

—

CE7

38000h–

3FFFFh

E0000h–

FFFFFh

1C0000h–

1FFFFFh

380000h–

3FFFFFh

700000h–

7FFFFFh

E00000h–

FFFFFFh

—

Maxim Integrated