Rockwell Automation 20D PowerFlex 700S AC Drives with Phase II Control Reference Manual - Manual (Page 180)

180 Rockwell Automation Publication PFLEX-RM003E-EN-E - January 2011
Chapter 1 Detailed Drive Operation
SynchLink This section contains information specific to PowerFlex 700S Phase II Control
SynchLink™ parameters and gives an example of setting up SynchLink using
DriveExecutive. Please refer to the
SynchLink System Design Guide, publication
1756-TD008 , for PowerFlex 700S SynchLink topologies, hardware, and wiring
details.
SynchLink Configuration
Parameter 904 [SL Node Cnfg] contains the following four bits:
• Bit 0 “Time Keeper” - This bit is turned on in the SynchLink master. Only
one node in a SynchLink network can be the time keeper.
• Bit 1 (Reserved) - Not used.
• Bit 2 “Sync Now” - This bit is turned on and all other bits off in the
SynchLink Followers.
• Bit 3 “Reset SL” - This bit can be turned on to reset SynchLink after a
SynchLink configuration change instead of cycling power on the drive.
SynchLink data is transmitted as a combination of direct and buffered data.
Parameters 905 [SL Rx CommFormat] and 910 [SL Tx CommFormat] set the
format for the receive and transmit data. The following tables show the different
formats for transmit and receive data and the respective SynchLink fiber-optic
update rates for the direct and buffered data.
Table 27 - Receive Data
Table 28 - Transmit Data
ATTENTION: You cannot redefine a position when using SynchLink to
communicate from a ControlLogix 1756 synch module to a PowerFlex 700S
Phase II drive.
Parameter 905
[SL Rx CommFormat] # of Direct Words Direct Word Update # of Buffered Words Buffered Word Update
7 2 50 µSec 18 0.5 ms
9 4 50 µSec 8 0.5 ms
17 4 50 µSec 18 1 ms
Parameter 910
[SL Tx CommFormat] # of Direct Words
Direct Word Update # of Buffered Words Buffered Word Update
7 2 50 µSec 18 0.5 ms
9 4 50 µSec 8 0.5 ms
17 4 50 µSec 18 1 ms