Rockwell Automation 1772-LP3 PLC - 2/30 Programmable Controller Programming and Operations Manual - Manual (Page 191)

Block Transfer
Chapter 10
10Ć8
During the program scan when input switch 113/02 is closed, the
instruction is enabled and read bit 012/17 is set to 1. In the next scan of
the output image table, the upper byte data of word address 012 is sent
to the module. The module responds that it is ready for transfer. The
processor interrupts the output image table scan and starts searching the
timer/counter accumulated area of the data table. It finds the module
address 121 in word address 030 and the file address, 060, in word
address 130.
The processor then transfers the data from the module into the 8-word
file beginning at word address 060 through 067. At the completion of the
transfer, done bit 112/17 is set to 1. The processor then completes the
I/O scan.
Under certain conditions, it may be desirable to transfer part of a file rather
than the entire file. For example, a processor could be programmed to read
the first two or three channels of an analog input module periodically but
read all channels less frequently. To do this, two or more block transfer
read instructions would be used: one for each desired transfer length
starting at the same first word. The read instructions would have the same
module address, data address and file address but different block lengths.
The size of the file would equal the largest transfer.
When two or more block transfer instructions have a common module
address, careful programming is required to compensate for the following
possible situations:
First, during any program scan, data in the output image table byte can be
changed alternately by each successive block transfer instruction having a
common module address. The enable bit can be turned on or off alternately
according to the true or false condition of the rungs containing these
instructions. The on or off status of the last rung will govern whether the
transfer will occur.
Second, the block length can be changed alternately in accordance with
the block lengths of the enabled instructions. The block length of the last
enabled block transfer instruction having a common module address will
govern the number of words transferred.
10.6
Multiple Reads of Different
Block Lengths from One
Module