Cirrus Logic EP73xx - Manual (Page 96)

9-6 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
LCD Interface
9
Hardware Interface
DD3 - DD0 carries the data that is output from the gray scale palette registers. Data for
each pixel will begin with the first nibble (assuming 4 bpp) at the beginning of the
frame buffer which will correspond to the first pixel location as seen above. For 2 bpp
and 1 bpp, the same hardware interface applies.
Color LCDs
The EP73xx does not directly support color LCDs. However, with minimal external
logic and a slight modification to the LCD driver, color can be supported. There are
no changes required for the control registers, only the data stored in the frame buffer.
• Maximum 3,375 simultaneous color support (i.e. 15 different colors per
sub-pixel)
• 1/4 VGA color STN display maximum size
• 120 x 320 x 8 bpp VGA color TFT display maximum size.
The external hardware splits DD3 - DD0 to create 8 bits of information. Half of the data
will be routed through a shift register, the other half route to the LCD screen directly.
CL2 (pixel clock) is halved by means of a D-flip flop which is fed to both the LCD
screen and the shift register. The result is 8 bits of data present at the LCD screen at
the same time along with its pixel clock and remaining control signals. See
Application Note 179 for a complete schematic.
Figure 9-2. LCD Data to Pixel Mapping
640x240 LCD S creen
1,1 1,2 1,3 1,4 1,640
240,640 240,1
DD3 DD2 DD0 DD1