Cirrus Logic EP73xx - Manual (Page 56)

4-10 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
Interrupt Controller
4
UTXINT1: Internal UART1 transmit FIFO half-empty interrupt. The function
of this interrupt source depends on whether the UART1 FIFO is
enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART1
bit rate and line control register), this interrupt will be active when
there is no data in the UART1 TX data holding register and be
cleared by writing to the UART1 data register. If the FIFO is
enabled this interrupt will be active when the UART1 TX FIFO is
half or more empty, and is cleared by filling the FIFO to at least
half full. The FIFO is 16 bytes deep.
URXINT1: Internal UART1 receive FIFO half full interrupt. The function of
this interrupt source depends on whether the UART1 FIFO is
enabled. If the FIFO is disabled this interrupt will be active when
there is valid RX data in the UART1 RX data holding register and
be cleared by reading this data. If the FIFO is enabled this
interrupt will be active when the UART1 RX FIFO is half or more
full or if the FIFO is non empty and no more characters have been
received for a three character time out period. It is cleared by
reading all the data from the RX FIFO. The FIFO is 16 bytes deep.
UMSINT: Internal UART1 modem status changed interrupt. This interrupt
will be active if either of the two modem status lines (CTS or DSR)
change state. It is cleared by writing to the UMSEOI location.
SSEOTI: Synchronous serial interface end of transfer interrupt. This
interrupt will be active after a complete data transfer to and from
the external ADC has been completed. It is cleared by reading the
ADC data from the SYNCIO register.
Interrupt Mask Register 1 (INTMR1)
Address: 0x8000.0280, Read / Write
Definition: This interrupt mask register is a 32-bit read/write register, used to
selectively enable any of the first 16 interrupt sources within the
EP73xx. Interrupts associated with bits 0 through 3 generate a fast
interrupt request to the ARM720T processor (FIQ), causing a jump
to processor virtual address 0000.001C. All other interrupts generate
a standard interrupt request (IRQ), causing a jump to processor
virtual address 0000.0018. Set the appropriate bit in this register to
enable the corresponding interrupt. All bits are cleared by a system
reset. Consult the bit definitions for INTSR1 for information about
interrupts associated with each mask bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSEOTI UMSINT URXINT1 UTXINT1 TINT RTCMI TC2OI TC1OI EINT3 EINT2 EINT1 CSINT MCINT WEINT BLINT EXTFIQ