Cirrus Logic EP73xx - Manual (Page 16)

1-2 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
Introduction
1
• Two 16-bit general purpose timer counters
• 32-bit RTC (Real-Time-Clock) timer and comparator
• Dedicated LED flasher pin driven from the RTC with programmable duty
ratio (Multiplexed with GPIO pin)
• Two synchronous serial interfaces for Micro-wire or SPI interfaces such as
ADCs, one supporting both the master and slave and other supporting
only master mode.
• Two programmable PWM (Pulse Width Modulation) interfaces
• SDRAM interface for direct interface to a maximum of two external banks
of SDRAM memory. Each bank can be up to 256 Mbit in size and
configurable for 32 or 16-bit wide accesses.
• PLL (Phase Lock Loop) oscillator for generating core speeds of 18-90 MHz
from an external 3.6864 MHz crystal.
• Low power 32.768 kHz RTC (Real Time Clock)
• MaverickKey - Unique and Random IDs for SDMI compliance
Memory Map and Register List
The lower 2 GByte of the address space is allocated to memory. The 64 MByte of
address space from 0xC000.0000 to 0xCFFF.FFFF is allocated to SDRAM. About
1.5 GBytes of address space, less 8 Kbytes for internal registers, is not accessible in the
EP73xx. The MMU in the EP73xx should be programmed to generate an abort
exception for access to this area.
Internal peripherals are addressed through a set of internal memory locations from
hex address 0x8000.0000 to 0x8000.3FFF. These are known as the internal registers in
the EP73xx. In
Table 1-1 also shows how the 4-Gbyte address range of the ARM720T
processor (as configured within this chip) is mapped in the EP73xx. The external boot
ROM is not fully decoded (i.e., the boot code will repeat within the 256-Mbyte space
from 0x7000.0000 to 0x8000.0000). See
Table 6-1 on page 6-2 for the memory map
when booted from on-chip boot ROM. The SRAM is fully decoded up to a maximum
size of 48 Kbytes. Access to any location above this range will be wrapped to within
the range.
Global Memory Map
Table 1-1: EP73xx Memory Map in External Boot Mode
Address Contents Size
0xF000.0000 Reserved 256 Mbytes
0xE000.0000 Reserved 256 Mbytes
0xD000.0000 Reserved 256 Mbytes
0xC000.0000 SDRAM 64 Mbytes