Cirrus Logic EP73xx - Manual (Page 106)

11-2 EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
General Purpose I/O (GPIO)
11
Programming Example
;*******************************************************************
; Enable GPIO Port B as Outputs. Set pins 0-3 high 4-7 low
;*******************************************************************
DATADIR EQU 0xFF
PORTB EQU 0x0F
;
ldrb r1, =DATADIR
strb r1, [r12, #0x41] ; Set direction as output
ldrb r1, =PORTB
strb r1, [r12, #0x1] ; Set PORTB initial condition
;
Operational Overview
PADDR, PBDDR, and PEDDR determine the direction of each of the GPIOs in their
respective port. If set, the corresponding GPIO will be configured as an output. If
cleared, the GPIO is treated as an input.
PDDDR determines the direction of PORTD. Initial state is low (output). High sets
pins as inputs.
Values read from these register, when configured as inputs, reflect the external state of
the pin. Values written to these pins, i.e. logic 1, when configured as an output, will
cause the logic state change from 0 to 3.3 V DC. All bits are cleared by a system reset.
Multiplexed Pins
Port A can be used to detect a keyboard entry to generate one of several internal
conditions as mentioned in the keyboard interface discussion.
PD6 and PD7 are multiplexed with SDRAM byte masks SDQM0 and SDQM1
respectively. To be used as GPIOs, SYSCON3 bit 10 must be set.
Port E, at power-on-reset, pins [1:0] are read during power-on-reset determine the
memory width of the boot ROM to the CPU. See the boot ROM discussion for more
details. After boot up, these pins are treated as GPIOs only.
Register Descriptions
See “General Purpose I/O (GPIO) Register List” on page 11-1 and Operational
Overview.