Chapter 4, Interrupt controller, Introduction – Cirrus Logic EP73xx User Manual
Page 47: Features, Interrupt register list, Chapter 4. interrupt controller, Table 4-1: interrupt registers -1, Chapter 4 4 interrupt controller introduction
EP7309/11/12 User’s Manual - DS508UM4
4-1
Copyright Cirrus Logic, Inc. 2003
44
4
Chapter 4
4
Interrupt Controller
Introduction
Like most modern microprocessors, the EP73xx contains an interrupt controller to
manage both external and internal exceptions. When an expected or unexpected
event arises during the execution of a program (i.e. interrupt or memory fault) an
exception is generated. If more than one exception occurs at the same time, a fixed
priority system determines the order in which they are handled.
Features
• Interrupt requests received from 22 different sources
• Standard (IRQ) and Fast (FIQ) interrupt types
• Interrupts can be used to wake the CPU from IDLE or STANDBY
Interrupt Register List
Table 4-1: Interrupt Registers
Address
Name
Type
Size
Description
Page
0x8000.0240
INTSR1
RO
32
Interrupt Status
0x8000.1240
INTSR2
R/W
32
Interrupt Status
page 4-11
0x8000.2240
INTSR3
R/W
32
Interrupt Status
0x8000.0280
INTMR1
R/W
32
Interrupt Mask
0x8000.1280
INTMR2
R/W
32
Interrupt Mask
0x8000.2280
INTMR3
R/W
32
Interrupt Mask
0x8000.0600
BLEOI
R/W
---
Battery Low EOI
0x8000.0640
MCEOI
R/W
---
Media Change EOI
0x8000.0680
TEOI
R/W
---
Tick Watchdog EOI
0x8000.06C0
TC1EOI
R/W
---
TC1 EOI
0x8000.0700
TC2EOI
R/W
---
TC2 EOI
0x8000.0740
RTCEOI
R/W
---
RTC Match EOI
0x8000.0780
UMSEOI
R/W
---
UART1 Modem EOI