Boot code, Appendix a. boot code, Appendix a a boot code – Cirrus Logic EP73xx User Manual
Page 155

EP7309/11/12 User’s Manual - DS508UM4
A-1
Copyright Cirrus Logic, Inc. 2003
AA
A
Appendix A
A
Boot Code
00000000
uart_boot_base
00000000 E3A0C102 MOV
r12, #HwRegisterBase ; R12 = 0x80000000
00000004
00000004 E3A08201 MOV
r8, #InternalRamBase ; R8 = 0x10000000
00000008 E2889B02 ADD
r9, r8, #ImageSize ; R9 = 0x10000800
0000000C
0000000C
0000000C
0000000C
;;; First, initialize HW control of UART
0000000C
0000000C 00000480 Hw_UARTDR1
EQU
0x0480
0000000C
0000000C 000004C0 Hw_UBRLCR1
EQU
0x04c0
0000000C 00000017 Hw_BR9600
EQU
0x00000017
; 9600 baud divisor = 23
0000000C 0000000B Hw_BR9600_13 EQU
0x0000000b
; 9600 baud divisor = 11
0000000C 00060000 Hw_WRDLEN8
EQU
0x00060000
0000000C
0000000C E3A00C01 MOV
r0, #Hw_UART1EN ; Enable UART
00000010 E58C0100 STR
r0, [r12, #Hw_SYSCON]
00000014
00000014 E28C1D45 ADD
r1, r12, #Hw_SYSFLG2 ; (was LDR, ADD in 7111 code)
00000018 E5917000 LDR
r7, [r1]
; R7 = SYSFLG2
0000001C
0000001C E3170040 TST
r7, #Hw_CKMODE
00000020 13A0000B MOVNE
r0, #Hw_BR9600_13 ; Load 13 MHz value if bit set
00000024 03A00017 MOVEQ
r0, #Hw_BR9600 ; If not set, load other divisor
00000028 E3800806 ORR
r0, r0, #Hw_WRDLEN8 ; Insert 8-bit character mode
0000002C
0000002C E58C04C0 STR
r0, [r12, #Hw_UBRLCR1]
00000030
00000030 0000003C StartFlag EQU
‘<’
00000030 0000003E EndFlag EQU
‘>’
00000030
00000030
;;; Send ready signal
00000030 E3A0003C MOV
r0, #StartFlag
00000034 E58C0480 STR
r0, [r12, #Hw_UARTDR1]
00000038
00000038
;;; Receive the data
00000038
;;; Store bytes at R9 address, stop loop when R8 == R9
00000038
;;; Leaves R8 set to 0x10000800
00000038
00000038
;;; Wait for byte to be available
00000038
00000038
uart_ready_loop
00000038 E59C1140 LDR
r1, [r12, #Hw_SYSFLG] ; Spin, if Rx FIFO is empty