Cache, Tlb -5 cache -5 – Cirrus Logic EP73xx User Manual
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EP7309/11/12 User’s Manual - DS508UM4
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Copyright Cirrus Logic, Inc. 2003
CPU Core
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TLB
The TLB (Translation look-aside Buffer) is a 64-entry associative cache of recent
virtual address to physical address translations to eliminate a two-stage search for a
higher proportion of internal register or external bus accesses.
• Provides the translation and access permission information for memory
accesses
• For a TLB miss, the TLB walking hardware accesses the transition table
from physical memory to update itself (two-stage).
• If the TLB is full, a stored value will be over-written.
Cache
Cache is 4-way set associative with 8 Kbytes of mixed instruction and data, organized
as 512 lines of 4 words (16-byte). Connected directly to the core, cache only stores the
virtual address. Cache can only be used once the MMU is enabled. Once enabled, the
specific sections or pages of memory that are segmented can control whether cache or
write buffer is used for that region. Cache is disabled at power on reset. See
for cache organization.