Cirrus Logic EP73xx - Manual (Page 41)

EP7309/11/12 User’s Manual - DS508UM4 2-15
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Copyright Cirrus Logic, Inc. 2003
CPU Core
22
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2. Once nPOR goes high, the EP73xx will enter Standby State. In this state, the
PLL is not enabled and thus the CPU is not turned on. The WAKEUP signal
must be asserted
3. After nPOR goes high, the WAKEUP signal will be detected by the processor
after one to two seconds. After such time, the WAKEUP (active high) signal
can be detected but must be asserted high for a minimum of 125
µs
Note: IMPORTANT. nURESET must not be asserted during the period between
WAKEUP assertion and transition from Standby to Operating state. This will
cause the processor to enter an unknown state and require a system reset to
clear this condition.
4. Once the WAKEUP signal is detected internally, it first enters a deglitching
circuit which is the reason for the 125
µs duration. The PLL is then enabled
and the CPU turns on. WAKEUP signal is then ignored and will only be
read again after a nPOR assertion or power is cycled on the device at which
time the EP73xx will return to Standby. WAKEUP is also ignored during
Idle state.
5. Once the WAKEUP signal has been detected, a maximum of 250 ms will
elapse before the CPU is turned on and begins fetching the first instruction.
RESET
There are three asynchronous resets to the EP73xx: nPOR , nPWRFL , and nURESET . If
any of these are active, a system reset is generated internally. This will reset all
internal registers in the EP73xx except the RTC data and match registers. These
registers are only cleared by
nPOR .
Any reset will also reset the CPU and cause it to start execution at the reset vector
(address 0x0) when the EP73xx returns to the operating state.
Internal to the EP73xx, three different signals are used to reset the storage elements.
These are
nPOR , nSYSRES , and nSTDBY .
nPOR (active low) is the highest priority reset signal and is also the external signal
that forces the internal signals nSYSRE S and nSTDBY (equivalent to the external RUN
signal) active. nPOR will only be active after the EP73xx has first powered up and not
during any other resets. nPOR active will clear all flags in the status register except for
the cold reset flag (CLDFLG) which is bit 15 of the SYSFLG register.
nSYSRES (System Reset, active low) is generated internally to the EP73xx if nPOR ,
nPWRFL , or nURESET are active. It is the second highest priority reset signal, used to
asynchronously reset most internal registers in the EP73xx. nSYSRES (when active)
forces nSTDBY and RUN low which is the result of the CPU resetting and the EP73xx
going into Standby. This can be done without co-operation from the system software.
The nSTDBY and RUN signals are high when the EP73xx is in Operating or Idle state.
The nSTDBY will disable any peripheral block that is clocked from the CPU clock
except the RTC.